EEPROM device for increasing a coupling ratio and fabrication method thereof

An electrically erasable and programmable read-only (EEPROM) device comprising:

• a memory transistor and a selection transistor on a semiconductor substrate;
• the memory transistor including
• a memory gate oxide layer including a first segment of a first thickness, a second segment of a second thickness, and a tunneling third segment of a third thickness, the second thickness being thicker than the first thickness, and the third thickness being thinner than the first thickness,
• a memory floating gate, an insulating layer pattern, and a control gate which are sequentially formed, respectively on the memory gate oxide layer,
• a source region formed in the semiconductor substrate and aligned with respect to one sidewall of the floating gate and the control gate, and
• a floating junction region formed in the semiconductor substrate and aligned with respect to the other sidewall of the floating gate and the control gate and also extending under the second segment and tunneling third segment of the memory gate oxide layer,
• the first segment being positioned over a region in the semiconductor substrate located between a source region and the floating junction region;
• and
• the selection transistor including
• a selection gate oxide layer,
• a selection gate structure formed on the selection gate oxide layer, and
• a drain region formed in the semiconductor and with respect to one sidewall of the gate electrode structure;
• the floating junction region also being aligned with the other sidewall of the gate electrode structure of the selection transistor.