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US 7,256,445 B2Granted
Fabrication of an EEPROM cell with emitter-polysilicon source/drain regions
AssigneeAtmel Corporation
InventorMuhammad I. Chaudhry
Life of this patent
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Abstract
An EEPROM memory cell uses an emitter polysilicon film for fabricating shallow source/drain regions to increase a breakdown voltage of the wells. The wells are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.
Claims6
An integrated circuit comprising:
- a semiconductor substrate of a first conductivity type having a surface;
- first, second and third spaced-apart lightly doped second conductivity type dopant regions in the substrate surface that form first, second, and third source-drain regions;
- first and second spaced-apart gates, the first gate located above and between the first and second source-drain regions and spaced therefrom by an oxide layer interrupted by a thinner tunnel oxide region, with a higher conductivity dopant region in the substrate below the tunnel oxide region, the second gate above and between the second and third source-drain regions and spaced therefrom by the oxide layer, the first and second spaced-apart gates forming portions of an EEPROM cell;
- and
- first and second highly doped second conductivity type emitter regions located above the first and third source-drain regions, the two emitter regions each forming portions of bipolar transistor devices.
2 more elements
Dependencies are inferred from the claim text.