Semiconductor memory and method of manufacturing the same
AssigneeInnotech Corporation
InventorTakashi Miida
Life of this patent
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Abstract
A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a silicon substrate, a control gate, a pair of electrically isolated floating gates. Plural projections are formed in the P type silicon substrate, and a pair of N type diffusion regions as the source and the drain is formed in both sides of the projection. The control gate faces the projection via a fourth insulation layer. The side surface of the floating gates faces the side surfaces of the projection via a first insulation layer, and faces the control gate via a third insulation layer. The floating gate faces the diffusion region via the first insulation layer.
Claims20
A semiconductor memory in which plural cell transistors are formed on a one conductive type semiconductor substrate and arranged in a column direction and a row direction perpendicular to the column direction to form a two-dimensional matrix, the cell transistor comprising:
- a first projection having a pair of side surfaces formed in the semiconductor substrate;
- a pair of opposite conductive type regions formed in both sides of the first projection in the semiconductor substrate, the opposite conductive type regions serving as the source and the drain of the cell transistor;
- a first insulation layer provided in the surfaces of the opposite conductive type regions and the side surfaces of the first projection;
- a pair of floating gates each of which is electrically isolated, the floating gate facing the opposite conductive type region via the first insulation layer and having a side surface facing the first projection via the first insulation layer;
- a second insulation layer formed on the floating gates;
- a control gate that faces the floating gate via the second insulation layer;
- a third insulation layer formed in the area in which the side surface of the floating gate is not covered with the first insulation layer, the side surface of the floating gate facing the control gate via the third insulation layer;
- and
- a fourth insulation layer provided between the first projection and the control gate.
A semiconductor memory in which plural cell transistors are formed on a one conductive type semiconductor substrate and arranged in a column direction and a row direction perpendicular to the column direction to form a two-dimensional matrix, the cell transistor comprising:
- a first projection having a pair of side surfaces formed in the semiconductor substrate;
- a pair of opposite conductive type regions formed in both sides of the first projection in the semiconductor substrate, the opposite conductive type regions serving as the source and the drain of the cell transistor;
- a pair of floating gates each of which is electrically isolated, the floating gate being provided above the opposite conductive type region and having a side surface facing the projection;
- an insulator that covers the whole of the floating gate and the top side of the projection, the floating gate being electrically isolated by the insulator;
- and
- a control gate formed above the floating gate and the projection via the insulator, the side surface of the floating gate facing the projection and the control gate via the insulator.
Dependencies are inferred from the claim text.