Semiconductor memory cell having a trench and a planar selection transistor and method for producing the same

A semiconductor memory cell having a trench and a planar select transistor, the memory cell comprising:

• a substrate;
• a trench arranged in the substrate and having a trench inner wall with a lower region, a middle region and an upper region;
• a dielectric layer arranged in the lower region at the trench inner wall;
• a first insulation collar arranged at the trench inner wall in the middle and upper regions, the first insulation collar having an upper edge;
• a first filling of the trench comprising a conductive material in the lower and middle regions;
• a first insulation layer for forming an insulation cover, the first insulation layer being arranged in the trench on the conductive material in an upper region of the trench and being connected to the insulation collar;
• an opening the insulation collar, which
• a) is placed on one side of the trench, completely beneath the insulation layer;
• b) from the trench faces toward a first sate contact of the memory cell;
• c) is filled with the conductive material;
• a buried doped region in the substrate, the buried doped region being electrically conductively coupled to the conductive material in the opening in order to form a buried strap;
• a planar select transistor, having the first gate contact of a first word line, a first diffusion region and a second diffusion region;
• the first diffusion region being arranged in the substrate and being electrically conductively coupled to the buried doped region;
• the second diffusion region being arranged in the substrate and being electrically conductively connected to a bit line contact;
• wherein the second diffusion region, on the opposite side from the trench and the first gate contact, adjoins a second trench of a second semiconductor memory cell;
• and
• wherein the second trench of the second semiconductor memory cell, on a side facing the second diffusion region, has a second insulation collar and a second insulation layer connected to the second insulation collar, so that a second conductive material in the second trench is insulated from the second diffusion region of the first semiconductor memory cell.

An arrangement of a plurality of semiconductor memory cells directly adjoining one another, each memory cell having a trench and planar select transistor, each trench having a trench inner wall with a lower region, a middle region, and an upper region, the arrangement being configured such that:

• the semiconductor memory cells of the arrangement each have a relative orientation of the planar select transistor with respect to the trench in a substrate, the relative orientation in the memory cell array, being identical for the plurality of semiconductor memory cells;
• and wherein each memory cell in the plurality, of memory cells has a surface area of less than 8 F2, where F is the minimum feature size in lithographic projection, and wherein each memory cell comprises:
• a dielectric layer arranged in the lower region at the trench inner wall;
• a first insulation collar arranged at the trench inner wall in the middle and upper regions, the first insulation collar having an upper edge;
• a first filling of the trench comprising a conductive material in the lower and middle regions;
• a first insulation layer for forming an insulation cover, the first insulation layer being arranged in the trench on the conductive material in an upper region of the trench and being connected to the insulation collar;
• an opening in the insulation collar, which a) is placed on one side of the trench, completely beneath the insulation layer;
• b) from the trench faces toward a first gate contact of the memory cell;
• c) is filled with the conductive material;
• and
• a buried doped region in the substrate, the buried doped region being electrically conductively coupled to the conductive material in the opening in order to form a buried strap;
• wherein the planar select transistor comprises:
• the first gate contact of a first word line;
• a first diffusion region, the first diffusion region being arranged in the substrate and being electrically conductively coupled to the buried doped region;
• and a second diffusion region, the second diffusion region being arranged in the substrate and being electrically conductively connected to a bit line contact.

A semiconductor memory cell having a trench and a planar select transistor, the memory cell comprising:

• a substrate;
• a trench arranged in the substrate and having a trench inner wall with a lower region, a middle region and an upper region;
• a dielectric layer arranged in the lower region at the trench inner wall;
• a first insulation collar arranged at the trench inner wall in the middle and upper regions, the first insulation collar having an upper edge;
• a first filling of the trench comprising a conductive material in the lower and middle regions;
• a first insulation layer for forming an insulation cover, the first insulation layer being arranged in the trench on the conductive material in an upper region of the trench and being connected to the insulation collar;
• an opening in the insulation collar, which
• a) is placed on one side of the trench, completely beneath the insulation layer;
• b) from the trench faces toward a first gate contact of the memory cell;
• c) is filled with the conductive material;
• a buried doped region in the substrate, the buried doped region being electrically conductively coupled to the conductive material in the opening in order to form a buried strap;
• a planar select transistor, having the first gate contact of a first word line, a first diffusion region and a second diffusion region;
• the first diffusion region being arranged in the substrate and being electrically conductively coupled to the buried doped region;
• and
• the second diffusion region being arranged in the substrate and being electrically conductively connected to a bit line contact;
• wherein the first gate contact of a first word line has a first width, and in that a second word line, at a location within the memory cell above the insulation layer, has a second width, the first width being greater than the second width.

A semiconductor memory cell having a trench and a planar select transistor, the memory cell comprising:

• a substrate;
• a trench arranged in the substrate and having a trench inner wall with a lower region, a middle region and an upper region;
• a dielectric layer arranged in the lower region at the trench inner wall;
• a first insulation collar arranged at the trench inner wall in the middle end upper regions, the first insulation collar having an upper edge;
• a first filling of the trench comprising a conductive material in the lower and middle regions;
• a first insulation layer for forming an insulation cover, the first insulation layer being arranged in the trench on the conductive material in an upper region of the trench and being connected to the insulation collar;
• an opening in the insulation collar, which
• a) is placed on one side of the trench, completely beneath the insulation layer;
• b) from the trench faces toward a first gate contact of the memory cell;
• c) is filled with the conductive material;
• a buried doped region in the substrate, the buried doped region being electrically conductively coupled to the conductive material in the opening in order to form a buried strap;
• a planar select transistor, having the first gate contact of a first word line, a first diffusion region and a second diffusion region;
• the first diffusion region being arranged in the substrate and being electrically conductively coupled to the buried doped region;
• and
• the second diffusion region being arranged in the substrate and being electrically conductively connected to a bit line contact;
• wherein the memory cell is in each case isolated by precisely one isolation trench on each longitudinal side from an adjacent third semiconductor memory cell.