US 7,256,125 B2Granted

Method of manufacturing a semiconductor device

AssigneeRenesas Technology Corp.

InventorsKentaro Yamada, Masato Takahashi, Tatsuyuki Konagaya, Takeshi Katoh, Masaki Sakashita, Koichiro Takei, Yasuhiro Obara, Yoshio Fukayama

Life of this patent

Estimating the term…

patentgrep

Loading patent…

Abstract

For improving the reliability of a semiconductor device having a stacked structure of a polycrystalline silicon film and a tungsten silicide film, the device is manufactured by forming a polycrystalline silicon film, a tungsten silicide film and an insulating film successively over a gate insulating film disposed over the main surface of a semiconductor substrate, and patterning them to form a gate electrode having a stacked structure consisting of the polycrystalline silicon film and tungsten silicide film. The polycrystalline silicon film has two regions, one region formed by an impurity-doped polycrystalline silicon and the other one formed by non-doped polycrystalline silicon. The tungsten silicide film is deposited so that the resistivity of it upon film formation would exceed 1000 μΩcm.

Claims18

Dependent claims

A manufacturing method of a semiconductor device, comprising the steps of:

(a) providing a semiconductor substrate;
(b) forming an insulating film over the semiconductor substrate;
(c) forming a polycrystalline silicon film over the insulating film;
(d) forming a WxSiy film over the polycrystalline silicon film;
(e) patterning the WxSiy film and the polycrystalline silicon film;
and
(f) after the step (e), performing heat treatment,
wherein the step (c) comprises sub-steps of:
(c1) forming a second region of the polycrystalline silicon film over the insulating film;
and
(c2) forming a first region of the polycrystalline silicon film over the second region of the polycrystalline silicon film, with an impurity concentration of the first region of the polycrystalline silicon film being smaller than that of the second region of the polycrystalline silicon film,
wherein in the step (d), the WxSiy film is formed so as to satisfy y/x≧2, and
wherein the WxSiy film formed in the step (d) has a resistivity of 1000 μΩcm or greater and has a resistivity of 400 μΩcm or less after the heat treatment in the step (f).

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/923,045Filed 23 Aug 2004
Priority: JP 2003-29979325 Aug 2003
Published: US 2005/0048708 A13 Mar 2005
Granted: 14 Aug 2007
Term ends: Not estimatedThe source records don’t support an estimate.

Classification19 codes

H10B 41/40
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the peripheral circuit region
H10B 41/49
Simultaneous manufacture of periphery and memory cells: comprising different types of peripheral transistor
H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…