Method for reducing semiconductor die warpage
AssigneeChipPAC, Inc.
InventorsSeung Wook Park, Tae Woo Lee, Hyun Jin Park
Life of this patent
Estimating the term…
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AssigneeChipPAC, Inc.
InventorsSeung Wook Park, Tae Woo Lee, Hyun Jin Park
Estimating the term…
An anti-warpage backgrinding tape (11) is secured to the circuit side (12) of a semiconductor wafer (14). The backside (16) of the wafer is background. The backside of the wafer is secured to dicing tape (18) so that the anti-warpage backgrinding tape is exposed. The wafer is diced to create individual die structure (34). The die structure comprises semiconductor die (22) with anti-warpage tape elements (36) on circuit sides of the semiconductor die. A die structure is removed from the dicing tape. The backside of the die of the die structure is adhered to a substrate (24). The anti-warpage tape element is removed from the die. The anti-warpage backgrinding tape is preferably partially or fully transparent to permit sensing of guide markings on the wafer during wafer dicing. The adhesive is preferably a curable adhesive. The adhesion between the anti-warpage tape element and the chosen die may be reduced by the application of heat (38).
A method for reducing semiconductor die warpage comprising:
A method for reducing semiconductor die warpage comprising:
Dependencies are inferred from the claim text.