Detecting reordered side-effects

A method, comprising the steps of:

• while translating at least a segment of a first binary representation of a program from a first instruction set to a second binary representation in a second instruction set, distinguishing individual memory loads that are believed to be directed to well-behaved memory from memory loads that are believed to be directed to non-well-behaved memory device(s);
• while executing the second binary representation, identifying a load that was believed at translation time to be directed to well-behaved memory but that at execution time is found to be directed to non-well-behaved memory, based at least in part on an annotation encoded in a segment descriptor, and aborting the identified memory load, a segment descriptor being data for controlling address formation by designating a segment base address, a segment length, and segment access control information;
• and
• based at least in part on the identifying, re-executing at least a portion of the translated segment of the program in the first instruction set.

A method, comprising the steps of:

• translating at least a segment of a source program into an object program, the source program instructing a reference execution with a reference sequence of side-effects, the object program instructing an execution in which the sequence of side-effects differs from the reference side-effect sequence;
• during an execution of the object program on a computer, detecting a side-effect about to be committed to processor state in which the differing side-effect sequence may have a material effect on the execution of the program, and aborting the side-effect;
• establishing a program state equivalent to a state that would have occurred in the reference execution;
• and
• resuming execution of the program from the established state in an execution mode that reflects the reference side-effect sequence.

An apparatus, comprising:

• a binary translator programmed to translate at least a segment of a program from a first binary representation in a first instruction set to a second binary representation in a second instruction set, a sequence of side-effects in the second binary representation differing from a sequence of side-effects in the translated segment of the first binary representation;
• and
• instruction execution circuitry and/or software designed to
• identify cases during execution of the second binary representation in which the difference in sequence of side-effects may have a material effect on the execution of the program, before committing the side-effect to processor state, and aborting the side-effect;
• and
• to establish a program state equivalent to a state that would have occurred in the execution of the first binary representation, and to resume execution of the program from the established state in an execution mode that reflects the side-effect sequence of the first binary representation.