Test structures for feature fidelity improvement
AssigneeIntel Corporation
InventorsSeongtae Jeong, Yan Borodovsky
Life of this patent
Estimating the term…
Abstract
Systems and techniques for generating test structures. The test structures may conform to a set of design rules for a portion of an integrated circuit design. The test structures may include base figures, which may be in an enriched environment. For example, the test structures may include one or more additional figures such as surrounding figures, external figures, and/or symmetric figures. A correction algorithm for correcting a layout may be checked using a plurality of the test structures.
Claims50
A method comprising:
- accessing rules for generating test structures, wherein the test structures are used to test one or more correction algorithms for adding corrective features to a semiconductor part, the semiconductor part for patterning a portion of one or more integrated circuits;
- receiving information describing a base figure, the base figure representing a potential feature in the portion of the one or more integrated circuits, the base figure having an outer border of a first shape and a first size;
- generating, in accordance with the rules, information describing a second figure positioned proximate to the base figure, the second figure representing a second potential feature in the portion of the one or more integrated circuits;
- and
- making the information describing the second figure available to test the one or more correction algorithms as part of a test structure.
A method comprising:
- receiving one or more characteristics of base figures, each base figure representing a potential feature in a layer of an integrated circuit;
- automatically generating information describing a plurality of different test structures based on the base figures;
- storing the plurality of different test structures, wherein each of the plurality of different test structures is in accordance with layer design rules;
- and
- making the plurality of different test structures available to test an algorithm for ensuring that features of a reticle adequately reflect design intent.
An article comprising one or more storage media having stored thereon instructions that when executed by one or more machines results in operations, the operations comprising:
- receiving rules for generating test structures, wherein the test structures are used to test one or more correction algorithms for adding corrective features to a semiconductor part, the semiconductor part for patterning a portion of one or more integrated circuits;
- receiving information describing a base figure, the base figure representing a potential feature in the portion of the one or more integrated circuits, the base figure having an outer border of a first shape and a first size;
- generating, in accordance with the rules, information describing a second figure positioned proximate to the base figure, the second figure representing a second potential feature in the portion of the one or more integrated circuits;
- and
- making the information describing the second figure available to test the one or more correction algorithms as part of a test structure.
An article comprising one or more storage media having stored thereon instructions that when executed by one or more machines results in operations, the operations comprising:
- receiving one or more characteristics of base figures, each base figure representing a potential feature in a layer of an integrated circuit;
- automatically generating information describing a plurality of different test structures based on the base figures;
- storing the plurality of different test structures, wherein each of the plurality of different test structures is in accordance with the layer design rules;
- and
- making the plurality of different test structures available to test an algorithm for ensuring that features of a reticle adequately reflect design intent.
Dependencies are inferred from the claim text.