Input/output cells with localized clock routing

A computer-readable medium having a netlist description of a circuit, the netlist description suitable for use in a process for forming an integrated circuit on a layer of a seiniconductive material, the netlist description comprising:

• a. computer-readable code defining a plurality of library cells;
• and
• b. computer-readable code defining at least two input/output (I/O) cell instances, wherein each I/O) cell instance comprises:
• i. a clock input port at a first location within a bounding box of the I/O cell instance, wherein the bounding box describes a smallest area that encloses the I/O cell instance;
• ii. a clock output port at a second location within the bounding box of the I/O cell1 instance, wherein the first and second locations abut in abutting instances of the I/O cell instance;
• iii. a first clock path adapted to convey a clock signal through the I/O cell instance from the clock input port to the clock output port;
• iv. I/O circuitry, including a locked-loop circuit coupled to the clock input port;
• v. a second clock path adapted to convey the clock signal from the clock input port to the I/O circuitry;
• and
• vi. at least one buffer disposed in at least one of the first and second clock paths.

An integrated circuit comprising:

• a. first cell instance disposed within a first bounding box, wherein the first bounding box describes a first smallest area that encloses the first cell instance, the first cell instance including:
• i. a first clock input port located within the first bounding box;
• ii. a first clock output port located within the first bounding box;
• iii. a first buffer located within the first bounding box and having a first buffer input terminal and a first buffer output terminal;
• iv. a first conductive strip located within the first bounding box and extending between the first clock input port and the first buffer input terminal;
• v. a second conductive strip located within the first bounding box and extending between the first buffer output terminal and the first clock output port;
• vi. first locked-loop circuitry located within the first bounding box and having a first clock terminal;
• and
• vii. a third conductive strip located within the first bounding box and extending between the first clock input port and the first clock terminal of the first locked-loop circuitry;
• and
• b. a second cell instance disposed with a second bounding box, wherein the second bounding box describes a second smallest area that encloses the second cell instance, the second bounding box located adjacent the first bounding box, the second cell instance comprising the same circuit elements as the first cell instance including:
• i. a second clock input port located within the second bounding box;
• ii. a second clock output part located within the second bounding box;
• iii. a second buffer located within the second bounding box and having a second buffer input terminal and a second buffer output terminal;
• iv. a fourth conductive strip located within the second bounding box and extending between the second clock input port and the second buffer input terminal;
• v. a fifth conductive strip located within the second bounding box and extending between the second buffer output terminal and the second clock output port;
• vi. second locked-loop circuitry located within the second bounding box and having a second clock terminal;
• and
• vii. a sixth conductive strip located within the second bounding box and extending between the second clock input port and the second clock terminal of the second locked-loop circuitry.

A method of routing a clock path of an integrated circuit, the method comprising:

• a. creating a first data structure defining a functional block, the data structure specifying:
• i. a clock input port;
• ii. a clock output port;
• iii. a buffer having a buffer input terminal sad a buffer output terminal;
• iv. a first conductive strip extending between the clock input port and the buffer input terminal;
• v. a second conductive strip extending between the buffer output terminal and the clock output port;
• vi. locked-loop circuitry having a clock terminal;
• vii. a third conductive strip extending between the clock input port and the clock terminal of the locked-loop circuitry;
• and
• viii. a bounding box encompassing elements i-vii, wherein the bounding box describes a smallest area that encloses elements i-vii;
• b. incorporating the first data structure into a second data structure, the second data structure specifying a first physical location for a first instance of the functional block and a second physical location for a second instance of the functional block;
• c. forming the first and second instances on a semiconductor at the specified first and second physical locations;
• and
• d. routing a connection between the clock output port of the first instance and the clock input port of the second instance.