Timing convergence, efficient algorithm to automate swapping of standard devices with low threshold-voltage devices
AssigneeSun Microsystems, Inc.
InventorsUmesh Nair, Toshinari Takayanagi
Life of this patent
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Abstract
A method for optimizing low threshold-voltage (Vt) devices in an integrated circuit design. The method includes identifying paths and nodes within the integrated circuit design, determining node overlap within the integrated circuit design, calculating possible solutions for addressing timing violations within the integrated circuit design, choosing a solution for addressing timing violations, inserting low Vt devices at particular nodes of the integrated circuit design, and repeating the calculated possible solutions wherein choosing a solution and inserting low Vt devices at particular nodes to address timing violations within the integrated circuit design.
Claims24
A method for optimizing low threshold-voltage (Vt) devices in an integrated circuit design comprising:
- identifying paths and nodes within the integrated circuit design;
- determining node overlap within the integrated circuit design;
- calculating possible solutions for addressing timing violations within the integrated circuit design;
- choosing a solution for addressing timing violations;
- inserting low Vt devices at one or more overlapping nodes of the integrated circuit design;
- and,
- repeating the calculating possible solutions, the choosing a solution and the inserting of low Vt devices at particular nodes to address timing violations within the integrated circuit design.
A apparatus for optimizing low Vt devices in an integrated circuit design comprising:
- means for identifying paths and nodes within the integrated circuit design;
- means for determining node overlap within the integrated circuit design;
- means for calculating possible solutions for addressing timing violations within the integrated circuit design;
- means for choosing a solution for addressing timing violations;
- means for inserting low Vt devices at one or more overlapping nodes of the integrated circuit design;
- and,
- means for repeating the calculating possible solutions, the choosing a solution and the inserting low Vt devices at particular nodes to address timing violations within the integrated circuit design.
A system for optimizing low Vt devices in an integrated circuit design comprising:
- an identifying module, the identifying module identifying paths and nodes within the integrated circuit design;
- a determining module, the determining module determining node overlap within the integrated circuit design;
- a calculating module, the calculating module calculating possible solutions for addressing timing violations within the integrated circuit design;
- a choosing module, the choosing module choosing a solution for addressing timing violations;
- an inserting module, the inserting module inserting low Vt devices at one or more overlapping nodes of the integrated circuit design;
- and,
- a repeating module, the repeating module repeating the calculating possible solutions, the choosing a solution and the inserting low Vt devices at particular nodes to address timing violations within the integrated circuit design.
Dependencies are inferred from the claim text.