Accounting for the effects of dummy metal patterns in integrated circuits
AssigneeCypress Semiconductor Corporation
InventorsSanjay Rekhi, Michael La Bouff
Life of this patent
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Abstract
In one embodiment, a level in a process technology for an integrated circuit that has dummy metal patterns is represented as a level in a process model. The level of the process model may comprise a high-k dielectric to represent the dummy metal patterns. In the level of the process model, each metal line may be surrounded by a normal dielectric. If the process technology has voids or pockets of air in between the metal lines, then each void or air pocket may be placed in a normal dielectric in the process model. Among other advantages, this allows the process model to take into account the effects of the dummy metal patterns.
Claims13
A method of modeling an integrated circuit, the method comprising:
- representing metals as a high-k dielectric in a level of a process model;
- surrounding the metals with a normal dielectric in the level of the process model, the normal dielectric representing actual dielectric in an integrated circuit modeled by the process model;
- and
- using regions within the normal dielectric in the level of the process model to represent a void in the integrated circuit modeled by the process model, a width of the normal dielectric in the process model being based on a critical distance between the void and a metal adjacent to the void in the integrated circuit.
A process model for a process technology of an integrated circuit, the model comprising:
- a first level comprising a high-k dielectric for each level of the process technology that contains a metal accounting for a dummy metal pattern, the first level further comprising a plurality of metal lines, each of the metal lines being surrounded by a normal dielectric that is present with the metal lines in an integrated circuit modeled by the process model;
- and
- a void placed within the normal dielectric, wherein a dimension of the normal dielectric in the process model is based on a critical distance between the void and a metal line adjacent to the void in the integrated circuit.
A method of taking into account effects of dummy metal patterns in an integrated circuit, the method comprising:
- obtaining a cross-section of a process technology for the integrated circuit;
- determining a dimension of a normal dielectric surrounding a metal in a process model;
- creating the process model using information from the cross-section of the process technology and the dimension of the normal dielectric, the process model including a level representing a level of the process technology that has dummy metal patterns, the level of the process model comprising a high-k dielectric, the level of the process model comprising metal lines that represent metal lines in the level of the process technology, each metal line in the level of the process model being surrounded by a normal dielectric;
- and
- placing a void in the normal dielectric in the level of the process model to represent a void in the level of the process technology, wherein the dimension of the normal dielectric in the process model is based on a critical distance between the void and a metal adjacent to the void in the process technology.
Dependencies are inferred from the claim text.