US 7,254,790 B2 · Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loops

Abstract

A moment computation technique for general lumped R(L)C interconnect circuits with multiple resistor loops is proposed. Using the concept of tearing, a lumped R(L)C network can be partitioned into a spanning tree and several resistor links. The contributions of network moments from each free and the corresponding links can be determined independently. By combining the conventional moment computation algorithms and the reduced ordered binary decision diagram (ROBDD), the proposed method can compute system moments efficiently. Experimental results demonstrate that the proposed method can indeed obtain accurate moments and is more efficient than the conventional approach.

Claims3

Dependent claims

A method of moment computations comprising:

providing R(L)C interconnects of a high speed VLSI circuit with resistor loops;
constructing an assistant reduced ordered binary-decision diagram (ROBDD);
tearing the high speed VLSI circuit into an open circuits and corresponding Thevenin equivalent circuits;
calculating a kth-order moment model of the open circuit using a recursive moment calculator;
calculating zeroth-order moments of the Thevenin equivalent circuits;
using a superposition theorem for the calculated kth-order system moment model and the zeroth-order moments to obtain system moments of the high speed VLSI circuit;
and
saving the obtained system moments of the high speed VLSI circuit.

5 more elements

Dependencies are inferred from the claim text.

Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loops

Life of this patent

Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loops

Life of this patent

Abstract

Claims3