Discrete multi-tone (DMT) system and method that communicates a data pump data stream between a general purpose CPU and a DSP via a buffering scheme

A system for communicating DSL data symbols, the system comprising:

• a first processor wherein the first processor generates one or more DSL data symbols;
• and
• a second processor wherein the second processor receives the one or more DSL data symbols from the first processor and transmits the one or more DSL data symbols over a communication media;
• wherein the second processor transmits a redundant DSL data symbol over the communication media in response to the first processor being unable to timely provide a new DSL data symbol;
• wherein the system has two modes of operation, a first mode of operation being where the second processor dedicates X MIPS to processing data packets and a second mode of operation being where the second processor dedicates Y MIPS to processing the data packets wherein Y is less than X.

A method for communicating one or more DSL data symbols, the method comprising:

• generating the one or more DSL data symbols in a first processor;
• providing the one or more DSL data symbols to the second processor via a data bus;
• receiving the one or more DSL data symbols from the data bus and storing the one or more DSL data symbols in a buffer;
• retrieving the one or more DSL data symbols from the buffer and sequentially transmitting the one or more DSL data symbols from the second processor along a transmission line;
• determining if one or more new DSL data symbols are available in the buffer;
• transmitting one or more redundant DSL data symbols from the second processor along the transmission line if the one or more DSL data symbols are not available in the buffer;
• and
• correcting, when one or more new DSL data symbols are available in the buffer, state of the DSL transmission to compensate for previously communicating the one or more redundant DSL data symbols;
• wherein the method has two modes of operation, a first mode of operation being where the second processor dedicates X MIPS to prcessing data packets and a second mode of operation being where the second processor dedicates Y MIPS to processing the data packets wherein Y is less than X.