Built-in self test for memory arrays using error correction coding

A memory system, comprising:

• a memory array adapted to store input test data and output stored test data during a plurality of memory read and write test operations;
• a comparator coupled to the memory array to receive the input test data and the stored test data, the comparator adapted to compare the input test data and the stored test data for a plurality of bit positions, and to provide a corresponding error signal when the stored test data is not identical to the input test data for each bit position of the plurality of bit positions;
• an integrator coupled to the comparator to receive the corresponding error signal, the integrator adapted to maintain the corresponding error signal for each bit position during the plurality of test operations;
• and
• a test control circuit coupled to the integrator, the test control circuit adapted to provide a fail signal when a predetermined level of corresponding error signals have been provided for the plurality of bit positions.

A method of testing a memory array, the memory array adapted to store input test data and output stored test data during a plurality of memory read and write test operations, the method comprising:

• comparing the input test data and the stored test data for a plurality of bit positions;
• providing a corresponding error signal when the stored test data is not identical to the input test data for each bit position of the plurality of bit positions;
• maintaining the corresponding error signal for each bit position during the plurality of test operations;
• and
• providing a fail signal when a predetermined level of corresponding error signals have been provided for the plurality of bit positions.

A memory system, comprising:

• a memory array adapted to store input test data and output stored test data during a plurality of memory read and write test operations;
• a test data generator coupled to the memory array to provide the input test data, the test data generator adapted to generate a plurality of test patterns corresponding to the plurality of test operations, each test pattern of the plurality of test patterns adapted to detect single-bit errors;
• a comparator coupled to the test data generator to receive the input test data and coupled to the memory array to receive the stored test data, the comparator adapted to compare the input test data and the stored test data for a plurality of bit positions, and to provide a corresponding error signal when the stored test data is not identical to the input test data for each bit position of the plurality of bit positions, wherein the plurality of bit positions correspond to one or more data words, each data word having a plurality of data bits and a plurality of error correction bits;
• an integrator coupled to the comparator to receive the corresponding error signal, the integrator adapted to maintain the corresponding error signal for each bit position during the plurality of test operations;
• and
• a test control circuit coupled to the integrator, the test control circuit adapted to provide a fail signal when a predetermined level of corresponding error signals have been provided for the plurality of bit positions, the predetermined level of corresponding error signals corresponding to an error correction capability of a selected error correction code.