Methods and systems for semiconductor defect detection
AssigneePowerchip Semiconductor Corp.
InventorsTong-Yu Liu, Yen-Sheng Chang
Life of this patent
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Abstract
A method for semiconductor defect detection, applied to a wafer test in a semiconductor process. A defect test is implemented for generating redundant information. an abnormal test implemented for generating a first FBM. The redundant information is converted to a second FBM. The first and second FBMs are compared, thereby generating a third FBM according to comparison results.
Claims12
A system for semiconductor defect detection, applied to abnormal analysis for a semiconductor component, comprising:
- an abnormal test unit, implementing an abnormal test to the semiconductor component for generating a first fail bit map (FBM);
- a converting unit, converting redundant information generated through a defect test to a second FBM;
- and
- a comparison unit, comparing the first and second FBMs for generating a third FBM.
A method for semiconductor defect detection, applied to a wafer test in a semiconductor process, comprising:
- implementing a defect test for generating redundant information;
- implementing an abnormal test for generating a first FBM;
- converting the redundant information to a second FBM;
- and
- comparing the first and second FBMs for generating a third FBM.
A semiconductor process implementing a wafer test process, the wafer test process applied to abnormal analysis for a semiconductor component using a method for semiconductor defect detection, the method comprising:
- implementing a defect test for generating redundant information;
- implementing an abnormal test for generating a first FBM;
- converting the redundant information to a second FBM;
- and
- comparing the first and second FBMs for generating a third FBM.
Dependencies are inferred from the claim text.