Method and apparatus for testing circuit units to be tested with different test mode data sets
AssigneeInfineon Technologies AG
InventorErwin Thalmann
Life of this patent
Estimating the term…
Abstract
The invention provides a test apparatus for testing a circuit unit to be tested. In one embodiment, a circuit unit incorporating aspects of the invention includes a data memory bank (106) for storing test mode data which are fed via an address control terminal (201) and with which the circuit unit (101) to be tested can be tested, provision being made of at least one test mode bank (104a-104n) for providing at least one test mode data set (204a-204n) and at least one activation signal (205a-205n), at least one register bank (103a-103n) and a transfer device for transferring a test mode data set (204a-204n) from a register bank (103a-103n) to the data memory bank (106) in a manner dependent on the activation signal (205a-205n).
Claims19
A circuit unit having a test mode, the circuit unit comprising:
- a plurality of data memory units;
- an address control terminal being configured to to receive test mode data;
- at least one test mode data bank being connected to the address control terminal to receive the test mode data, the at least one test mode data bank for generating a test mode data set and an activation signal;
- at least one register bank being configured to receive the generated test mode data set and the activation signal, the at least one register bank for outputting the received test mode data set in response to the received activation signal;
- and
- a transfer device being configured to receive the outputted test mode data set, the transfer device further being configured to transfer the outputted test mode data set to the plurality of memory units.
A method of testing a circuit unit comprising:
- a) receiving test mode data through an address control terminal of the circuit unit;
- b) generating with at least one test mode data bank at least one test mode data set and at least one activation signal;
- c) receiving at an at least one register bank the at least one test mode data set and the at least one activation signal;
- d) transferring through a transfer device the at least one test mode data set received by the at least one register bank to a data memory bank in response to the at least one activation signal;
- and
- e) storing the transferred at least one test mode data set in the data memory bank.
A test configuration within a circuit unit having a plurality of data memory units comprising:
- an address control terminal for receiving test mode data;
- a first test mode data bank being configured to receive the test mode data, the first test mode data bank for generating a first test mode data set and a first activation signal based upon the received test mode data;
- a second test mode data bank being configured to receive the test mode data, the second test mode data bank for generating a second test mode data set and a second activation signal based upon the received test mode data;
- a first register bank being configured to receive the generated first test mode data set and the first activation signal, the first register bank for outputting the received first test mode data set in response to the received first activation signal;
- a second register bank being configured to receive the generated second test mode data set and the second activation signal, the second register bank for outputting the received second test mode data set in response to the received second activation signal;
- and
- a transfer device being configured to receive the outputted first test mode data set and further being connected to the second register bank to receive the outputted second test mode data set, the transfer device further being configured to transfer the outputted first test mode data set and the outputted second test mode data set to the plurality of memory units.
Dependencies are inferred from the claim text.