Flash memory test system and method capable of test time reduction
AssigneeSamsung Electronics Co., Ltd.
InventorsDong-Kyoo Park, Jong-Kook Kim, Jeong-Ho Bang, Sang-Young Choi, Eun-Sik Kim
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Abstract
A flash memory test system capable of test time reduction and an electrical test method using the same: The invention provides a parallel tester that includes a first memory and a second memory. The first and second memories are used to each supply different data to identical addresses within a plurality of DUTs, thereby making it possible to conduct in parallel tests such as trim tests, repair tests, and invalid block masking test. Thus parallel testing is done to replace testing that was previously done serially.
Claims19
A flash memory test system comprising:
- a test processor to control tests of semiconductor memory devices;
- a programmable power supply connected to and controlled by said test processor;
- a direct current (DC) parameter measurement unit connected to and controlled by said test processor;
- an algorithmic pattern generator connected to and controlled by said test processor, said algorithmic pattern generator having a first memory that stores failure information and a second memory that stores failure address information corresponding to the failure information of the first memory, whereby different data can be supplied to identical addresses in each of a plurality of Devices Under Test (DUTs) during a parallel test of a specific item;
- a timing generator connected to and controlled by said test processor;
- pin electronics connected to and controlled by said test processor, and internally having a driver and a comparator;
- and
- a wave shape formatter that processes information supplied from the algorithmic pattern generator and the timing generator, and supplies the processed information to the pin electronics.
A method of reducing the test time of flash memory devices comprising:
- conducting a function test of a semiconductor memory device by a parallel test system;
- storing failure information in a particular address of a first memory, said address corresponding to the address of the failure in the DUT;
- searching the first memory and storing failure address information in a second memory within the tester;
- and
- conducting the parallel test by supplying respectively different data to identical addresses of the DUTs, using the information stored in the first and second memories during the function test of a specific item.
A method of testing flash memory devices utilizing an algorithmic pattern generator that includes a first memory and a second memory, said method comprising:
- testing a plurality of DUTs by a parallel test system;
- storing failure information in a particular address of the first memory of the tester once a failure is found in the DUT during a parallel function test, said particular address corresponding to the address of the failure in the DUT;
- searching the failure information of the first memory, and storing the information of the failure address in the second memory;
- and
- conducting the parallel test that supplies different data to the identical addresses of a plurality of DUTs, using the data stored in the first and second memories.
Dependencies are inferred from the claim text.