Data compression read mode for memory testing

A data compression read apparatus in a memory device, the apparatus comprising:

• a first series of bit match circuits that generates a first match signal for indicating whether a predetermined bit position of each of a plurality of data words are a logical zero;
• a second series of bit match circuits that generates a second match signal for indicating whether the predetermined bit position of each of the plurality of data words are a logical one, wherein each bit match circuit comprises:
• a first transistor having an input connection, an output connection, and a first control gate;
• a second transistor coupled in parallel to the first transistor, the second transistor having a second control gate;
• a third transistor coupled between ground and the output connection, the third transistor having a third control gate;
• and
• a control input circuit having an enable signal and the predetermined bit as inputs, the control input circuit generating a control signal output coupled to the first, second, and third control gates such that an input signal on the input connection is routed to the output connection when the control signal is in one state and the output connection is grounded when the control signal is in a second state;
• and
• an output buffer circuit coupled to the first and second series of bit match circuits such that the output buffer outputs the predetermined bit when either the first or the second match signals indicate a true state and the output buffer being in a high impedance state in response to the first or second match signals indicating a false state.

A data compression read apparatus in a flash memory device, the apparatus comprising:

• a first series of bit match circuits that generates a first match signal for indicating when a predetermined bit position of each of a plurality of data words are a logical zero, the first series of bit match circuits comprising a plurality of bit match circuits each having a complementary transfer gate controlled by a logical combination of the predetermined bit and an enable signal;
• a second series of bit match circuits that generates a second match signal for indicating when the predetermined bit position of each of the plurality of data words are a logical one, the second series of bit match circuits comprising a plurality of bit match circuits each having a complementary transfer gate controlled by a logical combination of the predetermined bit and the enable signal;
• a logical OR operation having inputs coupled to the first and second match signals, the logical OR operation generating a true indication when one of the first or second match signals indicates a true state and a false indication otherwise;
• and
• an output buffer circuit coupled to the logical OR operation such that the output buffer passes the predetermined bit in response to the true indication and the output buffer being in a high impedance state in response to the false indication.

A bit match circuit comprising:

• a first transistor having an input connection, an output connection, and a first control gate;
• a second transistor coupled in parallel to the first transistor, the second transistor having a second control gate;
• a switching device coupled between ground and the output connection, the switching device having a control input;
• and
• a control input circuit having an enable signal and a predetermined data bit as inputs, the control input circuit generating a control signal output coupled to the first and second control gates and the control input such that an input signal on the input connection is routed to the output connection when the control signal is in a first logical state and the output connection is grounded when the control signal is in an inverse logical state.

A method for performing a compressed read operation in a memory device having an output buffer, the method comprising:

• combining a first plurality of bit match circuits in series such that each bit match circuit is coupled to a predetermined bit of a plurality of data words, each bit match circuit having a complementary transfer gate controlled by a logical combination of the predetermined bit and an enable signal;
• combining a second plurality of bit match circuits in series such that each bit match circuit is coupled to the predetermined bit of the plurality of data words, each bit match circuit having a complementary transfer gate controlled by a logical combination of the predetermined bit and the enable signal;
• performing a logical zero bit match operation on a plurality of predetermined bits in the predetermined bit location with the first plurality of bit match circuits;
• performing a logical one bit match operation on the plurality of predetermined bits with the second plurality of bit match circuits;
• if the plurality of predetermined bits in each of the plurality of data words have a same value, enabling transfer of the value through the output buffer;
• and
• if the plurality of predetermined bits in each of the plurality of data words do not have the same value, causing the output buffer to be in a high impedance state.

An electronic system comprising:

• a processor that controls the operation of the electronic system;
• and
• a memory device coupled to the processor, the memory device having a data compression read apparatus comprising:
• a first circuit that generates a first match signal when a data bit in a predetermined bit position of each of a plurality of data words are a logical zero, the first circuit comprising a plurality of bit match circuits each having a complementary transfer gate controlled by a logical combination of the predetermined bit and an enable signal;
• a second circuit that generates a second match signal when the data bit in the predetermined bit position of each of the plurality of data words are a logical one, the second circuit comprising a plurality of bit match circuits each having a complementary transfer gate controlled by a logical combination of the predetermined bit and the enable signal;
• and
• an output buffer circuit that either passes the data bit or is in a high impedance state in response to the first or second match signals.

A data compression read apparatus in a memory device, the apparatus comprising:

• a first series of bit match circuits that generates a first match signal for indicating when a predetermined bit position of each of a plurality of data words are a logical zero;
• a second series of bit match circuits that generates a second match signal for indicating when the predetermined bit position of each of the plurality of data words are a logical one;
• a plurality of propagation repeater circuits that regenerate the first and second match signals, a first propagation repeater circuit coupled between a predetermined number of the first series of bit match circuits and a second propagation repeater circuit coupled between a predetermined number of the second series of bit match circuits;
• and
• an output buffer circuit coupled to the first and second series of bit match circuits such that the output buffer outputs the predetermined bit when either the first or the second match signals indicate a true state and the output buffer being in a high impedance state in response to the first or second match signals indicating a false state.

A method for performing a compressed read operation in a memory device having an output buffer, the method comprising:

• performing a bit match operation on a data bit at a predetermined bit of each word involved in the compressed read operation, the bit match operation performed by a complementary transfer gate controlled by a logical combination of the predetermined bit and an enable signal;
• if the data bits in each of the predetermined bit location in each word are equal, enabling transfer of the data bit through the output buffer;
• and
• if the data bits in each of the predetermined bit locations in each word are not equal, determining the predetermined bit location of the word that is causing an error condition.