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US 7,254,753 B2Granted
Circuit and method for configuring CAM array margin test and operation
AssigneeMicron Technology, Inc.
InventorDaniel R. Loughmiller
Life of this patent
Estimating the term…
Abstract
A test circuit for a content addressable memory (CAM) match detection circuit that permits testing of the margin of the match detection circuit. By applying various loads to the matchline and/or the discharge line, the match detection circuit demonstrates whether it can overcome the applied loads.
Claims64
A test circuit for testing a match detection circuit, said test circuit comprising:
- a test line for providing a load to the match detection circuit;
- and
- a switch for switchably coupling the test line to a first line of the match detection circuit to provide the load on the first line for testing whether the match detection circuit is correctly indicating either a match or mismatch.
A test circuit for a detection match circuit, said test circuit comprising:
- a test line being switchably coupled to a first line of a match detection circuit for providing a load to said match detection circuit to test match detection's circuit ability to either hold a value or discharge a value.
A test circuit for a match detection circuit, said test circuit comprising:
- a test circuit for providing a first load to said match detection circuit to test a margin of said match detection circuit.
A test circuit for testing a match detection circuit, said test circuit comprising:
- a test circuit controller;
- a plurality of test lines switchably coupled to a matchline of said match detection circuit to test a feature of said match detection circuit, wherein each of said plurality of test lines comprises:
- a load, wherein said load is a resistor;
- and
- a test line transistor for switchably coupling said load and said matchline for testing whether the match detection circuit is correctly indicating either a match or mismatch, a gate of said test line transistor coupled to said test circuit controller.
2 more elements
A test circuit for testing a match detection circuit, said test circuit comprising:
- a test circuit controller;
- a plurality of test lines switchably coupled to a matchline of said match detection circuit to test a feature of said match detection circuit, wherein each of said plurality of test lines comprises:
- a load, wherein said load is a voltage;
- and
- a test line transistor for switchably coupling said load and said matchline for testing whether the match detection circuit is correctly indicating either a match or mismatch, a gate of said test line transistor coupled to said test circuit controller.
2 more elements
A test circuit for testing a match detection circuit, said test circuit comprising:
- a test circuit controller;
- a decision circuit;
- a plurality of test lines switchably coupled to a discharge line of said match detection circuit to test a feature of said match detection circuit, wherein each of said plurality of test lines comprises:
- a load, wherein said load is a resistor;
- and
- a test line transistor for switchably coupling said load and said discharge line for testing whether the match detection circuit is correctly indicating either a match or mismatch, a gate of said test line transistor coupled to said test circuit controller.
3 more elements
A router, comprising:
- a content addressable memory (CAM) system, said CAM system comprising:
- a test circuit for testing a match detection circuit, said test circuit comprising:
- a test circuit controller;
- a plurality of test lines switchably coupled to a matchline of said match detection circuit to test a feature of said match detection circuit, wherein each of said plurality of test lines comprises:
- a load, wherein said load is a resistor;
- and
- a test line transistor for switchably coupling said load and said matchline for testing whether the match detection circuit is correctly indicating either a match or mismatch, a gate of said test line transistor coupled to said test circuit controller.
4 more elements
A router, comprising:
- a content addressable memory (CAM) system, said CAM system comprising:
- a test circuit for testing a match detection circuit, said test circuit comprising:
- a test circuit controller;
- a plurality of test lines switchably coupled to a matchline of said match detection circuit to test a feature of said match detection circuit, wherein each of said plurality of test lines comprises:
- a load, wherein said load is a voltage;
- and
- a test line transistor for switchably coupling said load and said matchline for testing whether the match detection circuit is correctly indicating either a match or mismatch, a gate of said test line transistor coupled to said test circuit controller.
4 more elements
A router, comprising:
- a content addressable memory (CAM) system, said CAM system comprising:
- a test circuit for testing a match detection circuit, said test circuit comprising:
- a test circuit controller;
- a decision circuit;
- a plurality of test lines switchably coupled to a discharge line of said match detection circuit to test a feature of said match detection circuit, wherein each of said plurality of test lines comprises:
- a load, wherein said load is a resistor;
- and
- a test line transistor for switchably coupling said load and said discharge line for testing whether the match detection circuit is correctly indicating either a match or mismatch, a gate of said test line transistor coupled to said test circuit controller.
5 more elements
A integrated circuit chip, comprising:
- a content addressable memory (CAM) system, said CAM system comprising:
- a test circuit for testing a match detection circuit, said test circuit comprising:
- a test circuit controller;
- a plurality of test lines switchably coupled to a matchline of said match detection circuit to test a feature of said match detection circuit, wherein each of said plurality of test lines comprises:
- a load, wherein said load is a resistor;
- and
- a test line transistor for switchably coupling said load and said matchline for testing whether the match detection circuit is correctly indicating either a match or mismatch, a gate of said test line transistor coupled to said test circuit controller.
4 more elements
A integrated circuit chip, comprising:
- a content addressable memory (CAM) system, said CAM system comprising:
- a test circuit for testing a match detection circuit, said test circuit comprising:
- a test circuit controller;
- a plurality of test lines switchably coupled to a matchline of said match detection circuit to test a feature of said match detection circuit, wherein each of said plurality of test lines comprises:
- a load, wherein said load is a voltage;
- and
- a test line transistor for switchably coupling said load and said matchline for testing whether the match detection circuit is correctly indicating either a match or mismatch, a gate of said test line transistor coupled to said test circuit controller.
4 more elements
A integrated circuit chip, comprising:
- a content addressable memory (CAM) system, said CAM system comprising:
- a test circuit for testing a match detection circuit, said test circuit comprising:
- a test circuit controller;
- a decision circuit;
- a plurality of test lines switchably coupled to a discharge line of said match detection circuit to test a feature of said match detection circuit, wherein each of said plurality of test lines comprises:
- a load, wherein said load is a resistor;
- and
- a test line transistor for switchably coupling said load and said discharge line for testing whether the match detection circuit is correctly indicating either a match or mismatch, a gate of said test line transistor coupled to said test circuit controller.
5 more elements
A processor system, comprising:
- a processor;
- a content addressable memory (CAM) system, said CAM system comprising:
- a test circuit for testing a match detection circuit, said test circuit comprising:
- a test circuit controller;
- a plurality of test lines switchably coupled to a matchline of said match detection circuit to test a feature of said match detection circuit, wherein each of said plurality of test lines comprises:
- a load, wherein said load is a resistor;
- and
- a test line transistor for switchably coupling said load and said matchline for testing whether the match detection circuit is correctly indicating either a match or mismatch, a gate of said test line transistor coupled to said test circuit controller.
5 more elements
A processor system, comprising:
- a processor;
- a content addressable memory (CAM) system, said CAM system comprising:
- a test circuit for testing a match detection circuit, said test circuit comprising:
- a test circuit controller;
- a plurality of test lines switchably coupled to a matchline of said match detection circuit to test a feature of said match detection circuit, wherein each of said plurality of test lines comprises:
- a load, wherein said load is a voltage;
- and
- a test line transistor for switchably coupling said load and said matchline for testing whether the match detection circuit is correctly indicating either a match or mismatch, a gate of said test line transistor coupled to said test circuit controller.
5 more elements
A processor system, comprising:
- a processor;
- a content addressable memory (CAM) system, said CAM system comprising:
- a test circuit for testing a match detection circuit, said test circuit comprising:
- a test circuit controller;
- a decision circuit;
- a plurality of test lines switchably coupled to a discharge line of said match detection circuit to test a feature of said match detection circuit, wherein each of said plurality of test lines comprises:
- a load, wherein said load is a resistor;
- and
- a test line transistor for switchably coupling said load and said discharge line for testing whether the match detection circuit is correctly indicating either a match or mismatch, a gate of said test line transistor coupled to said test circuit controller.
6 more elements
A method of testing a match detection circuit, comprising the steps of:
- switchably coupling a load to said match detection circuit;
- and
- applying said load to said match detection circuit for testing whether the match detection circuit is correctly indicating either a match or mismatch.
A method of testing a match detection circuit, comprising the step of:
- precharging a matchline of said match detection circuit;
- applying a load to said matchline to test a feature of the match detection circuit;
- comparing a stored bit in said match detection circuit with a comparand bit;
- and
- determining whether said matchline is pulled to ground when a mismatch occurs in said comparing step.
2 more elements
A method of testing a match detection circuit, comprising the step of:
- precharging a matchline of said match detection circuit;
- applying a load to said matchline to test a feature of the match detection circuit;
- comparing a stored bit in said match detection circuit with a comparand bit;
- and
- determining whether said matchline is pulled to ground when a match occurs in said comparing step.
2 more elements
A method of testing a match detection circuit, comprising the steps of:
- precharging a matchline of said match detection circuit;
- applying a load to a discharge line to test a feature of the match detection circuit;
- comparing a stored bit in said match detection circuit with a comparand bit;
- and
- determining whether said matchline is pulled to ground when a mismatch occurs in said comparing step.
2 more elements
A content addressable memory, comprising:
- a match detection circuit coupled to a match line and a discharge line;
- and
- a test circuit for testing said match detection circuit, said test circuit comprising:
- at least one test line for testing a feature of said match detection circuit, wherein said test line comprises:
- a resistance;
- and
- a test line transistor for selectively coupling said resistance between said matchline and a voltage source line for testing whether the match detection circuit is correctly indicating either a match or mismatch.
4 more elements
A content addressable memory, comprising:
- a match detection circuit coupled to a match line and a discharge line;
- and
- a test circuit for testing said match detection circuit, said test circuit comprising:
- at least one test line for testing a feature of said match detection circuit, wherein said test line comprises:
- a resistance;
- and
- a test line transistor for selectively coupling said resistance between said match line and a ground line for testing whether the match detection circuit is correctly indicating either a match or mismatch.
4 more elements
A content addressable memory, comprising:
- a match detection circuit coupled to a match line and a discharge line;
- and
- a test circuit for testing said match detection circuit, said test circuit comprising:
- at least one test line for testing a feature of said match detection circuit, wherein said test line comprises:
- a resistance;
- and
- a test line transistor for selectively coupling said resistance between said discharge line and a ground line for testing whether the match detection circuit is correctly indicating either a match or mismatch.
4 more elements
Dependencies are inferred from the claim text.