Method and apparatus for using a fault tolerant memory in processor testing and design
AssigneeSun Microsystems, Inc.
InventorsPradeep Kaushik, Dennis Wendell
Life of this patent
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Abstract
An apparatus and method for controlling and providing a robust, single entry cache memory is described in connection with an on-board cache memory integrated with a microprocessor. By implementing the single entry cache memory in a redundancy array of the cache memory, CPU debug procedures may proceed independently of the cache debug by disabling part of the cache memory and enabling a dedicated single entry cache in the redundancy array. Use of a cache redundancy array for the single entry cache imposes no area or latency penalties because the existing cache redundancy array already matches the latency of the cache.
Claims19
A processor for executing instructions, comprising:
- a CPU for executing the instructions;
- a cache memory comprising a main array and a redundancy array, said redundancy array comprising a limited entry cache;
- a cache mode select unit configured to disable the main array and enable only the limited entry cache to perform cache operations for the CPU;
- a first data output line for reading data from the cache memory in an operative mode;
- and
- a second data output line for reading data from the limited entry cache in a test mode.
A method for testing a processor having on-chip cache, comprising:
- providing a processor having an on-chip cache comprising a main cache array and a redundancy cache array;
- issuing a set command for setting a mode of operating the on-chip cache of the processor, the set command being a bit value for disabling or enabling access to the main cache array;
- switching the mode of operating the on-chip cache of the processor to enable testing of the processor using only the redundancy cache array when the main cache array is disabled;
- performing cache operations for testing of the processor through a limited entry cache in the redundancy cache array;
- reading data from the on-chip, cache in an operative mode;
- and
- reading data from the limited entry cache in a test mode.
An integrated circuit, comprising:
- a test circuit requiring access to a cache memory;
- the cache memory comprising a first array and a second array;
- a selection circuit for disabling the first array and enabling only the second array during testing of the test circuit;
- wherein the test circuit is coupled to only the second array for any cache memory access requirements during testing of the test circuit;
- a first data output line for reading data from the cache memory in an operative mode;
- and
- a second data output line for reading data from the second array in a test mode.
Dependencies are inferred from the claim text.