Attaining high availability through a power system branch architecture

Apparatus comprising:

• a plurality of devices, each device having a unique address represented by a separate plurality of address bits;
• logic for producing intermediate bits, the number of intermediate bits being fewer than the number of address bits, the intermediate bits being used to drive the address bits, some of the intermediate bits driving more than one address bit;
• wherein the logic comprises a first logic device and a second logic device;
• wherein the first logic device produces first intermediate bits, the first intermediate bits being used to drive a first set of the address bits, some of the first intermediate bits driving more than one of the first set of address bits;
• and
• wherein the second logic device produces second intermediate bits, the second intermediate bits being used to drive a second set of the address bits, some of the second intermediate bits being used to drive more than one of the second set of address bits.

A method comprising the steps of:

• providing a first device including a first reserved space;
• providing a second device including a second reserved space;
• providing a third device including a copy of the first reserved space;
• providing a fourth device including a copy of the second reserved space, each device having a unique address represented by a separate plurality of address bits;
• providing power to the first device and the second device via a first power branch;
• providing power to the third device and the fourth device via a second power branch;
• and
• producing intermediate bits, the number of intermediate bits being fewer than the number of address bits, the intermediate bits being used to drive the address bits, some of the intermediate bits driving more than one address bit;
• wherein each device is a Fibre Channel Arbitrated Loop device having an arbitrated loop physical address as the unique address of that device;
• and
• wherein the method further comprises the step of:
• generating multiple arbitrated loop physical address bits belonging to multiple arbitrated loop physical addresses in response to receipt of a particular intermediate bit, each of the multiple arbitrated loop physical address bits belonging to a different arbitrated loon physical address which uniquely corresponds to a particular Fibre Channel Arbitrated Loop device to provide consolidation of addressing in which the particular intermediate bit maps to the multiple arbitrated loon physical address bits.

A method comprising the steps of:

• providing a plurality of devices, each device having a unique address represented by a separate plurality of address bits;
• and
• producing intermediate bits, the number of intermediate bits being fewer than the number of address bits, the intermediate bits being used to drive the address bits, some of the intermediate bits driving more than one address bit;
• wherein the step of producing comprises:
• producing first intermediate bits, the first intermediate bits being used to drive a first set of the address bits, some of the first intermediate bits driving more than one of the first set of address bits, and
• producing second intermediate bits, the second intermediate bits being used to drive a second set of the address bits, some of the second intermediate bits being used to drive more than one of the second set of address bits.

Apparatus comprising:

• a plurality of devices, each device having a unique address represented by a separate plurality of address bits;
• logic for producing intermediate bits, the number of intermediate bits being fewer than the number of address bits, the intermediate bits being used to drive the address bits, some of the intermediate bits driving more than one address bit;
• wherein each device is a Fibre Channel Arbitrated Loop device having an arbitrated loop physical address as the unique address of that device;
• and
• wherein the apparatus further comprises:
• a programmable logic device coupled to the logic for producing the intermediate bits, the programmable logic device being configured to (i) receive a particular intermediate bit from the logic and (ii) generate multiple arbitrated loop physical address bits belonging to multiple arbitrated loop physical addresses in response to receipt of that particular intermediate bit, each of the multiple arbitrated loop physical address bits belonging to a different arbitrated loop physical address which uniquely corresponds to a particular Fibre Channel Arbitrated Loop device to provide consolidation of addressing in which the particular intermediate bit maps to the multiple arbitrated loop physical address bits.

A method comprising the steps of:

• providing a plurality of devices, each device having a unique address represented by a separate plurality of address bits;
• and
• producing intermediate bits, the number of intermediate bits being fewer than the number of address bits, the intermediate bits being used to drive the address bits, some of the intermediate bits driving more than one address bit;
• wherein each device is a Fibre Channel Arbitrated Loop device having an arbitrated loop physical address as the unique address of that device;
• and
• wherein the method further comprises the step of:
• generating multiple arbitrated loop physical address bits belonging to multiple arbitrated loop physical addresses in response to receipt of a particular intermediate bit, each of the multiple arbitrated loop physical address bits belonging to a different arbitrated loop physical address which uniquely corresponds to a particular Fibre Channel Arbitrated Loop device to provide consolidation of addressing in which the particular intermediate bit maps to the multiple arbitrated loop physical address bits.