US 7,254,735 B2Granted

Data processing system with block control circuits using self-synchronization handshaking and local clock/power control based on detected completion within subblocks

AssigneeRenesas Technology Corp.

InventorHidehiro Takata

Life of this patent

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Abstract

It is an object to obtain a self-synchronization type block processing apparatus which does not need to optimize a clock path to be distributed to each block in a clock phase management at an upper level, and can suppress an increase in a circuit scale and can minimize an increase in a design period by circuit tuning. A local block control circuit comprises an end detecting section for receiving a plurality of complete signals, a transfer control section for generating a stop signal having a negative logic to determine whether or not a system clock is supplied to a processing block upon receipt of an end signal output from the end detecting section, the system clock and a handshaking control signal, and a logical AND gate for generating an in-block clock based on the stop signal having the negative logic which is output from the transfer control section and the system clock.

Claims8

Dependent claims

A data processing system for processing data via a plurality of processing blocks, comprising:

a plurality of block control circuits provided corresponding to said respective processing blocks,
said block control circuits controlling corresponding processing blocks by a clock synchronization respectively and transferring a handshaking control signal with other block control circuits, thereby controlling a data transfer between said processing blocks by self-synchronization type handshaking,
wherein each said processing block has a plurality of subblocks and said data are processed via said plurality of subblocks,
at least one of said plurality of subblocks outputs a complete signal indicating that a data processing is completed, and
each of said plurality of block control circuits has:
an end detecting section for detecting an end of a data processing in a corresponding one of said processing blocks upon receipt of said complete signal output from said at least one of said plurality of subblocks;
and
a transfer control section for receiving a detection result signal output from said end detecting section to control supply and stop of a clock for a corresponding one of said processing blocks in response to a stop signal created based on said detection result signal and for transferring said handshaking control signal to control a data transfer between said plurality of processing blocks by self-synchronization type handshaking.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/672,640Filed 26 Sep 2003
Priority: JP 2003-11671622 Apr 2003
Published: US 2004/0215994 A128 Oct 2004
Granted: 7 Aug 2007
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 1/3287
Power saving characterised by the action undertaken: by switching off individual functional units in the computer system
G06F 1/12
Generating or distributing clock signals or signals derived directly therefrom: synchronisation of different clock signals provided by a plurality…
G06F 1/3203
Means for saving power: power management, i.e. event-based initiation of a power-saving mode
Y02D 10/00
Energy efficient computing