Information processor with suppressed cache coherence in low power mode

A computer program product comprising computer executable instructions, stored on a computer readable medium, for signaling an information processor having a normal-operation mode in which coherence control is performed for making data in a cache memory of a processor identical to data in a main memory and a power-saving mode in which said coherence control is suppressed to lower the power consumption from power consumption in said normal-operation mode, the computer program product comprising:

• instructions for causing the information processor to enter said normal-operation mode when an input/output device accesses said main memory in said power-saving mode;
• attribute setting instructions for setting a device area of said main memory to a non-cacheable attribute for exempting said device area from said coherence control even in said normal-operation mode, said device area being an area of the main memory accessed by the input/output device;
• and
• operation mode setting instructions for allowing said input/output device to access said device area while keeping the operation mode of said information processor in said power-saving mode when said input/output device requests access to said device area in said power-saving mode.

A control circuit for controlling mode selection in an information processor having a normal-operation mode in which coherence control is performed for making data in a cache memory identical to data in a main memory and a power-saving mode in which said coherence control is suppressed to lower the power consumption from power consumption in said normal-operation mode and entering said normal-operation mode when an input/output device accesses said main memory in said power-saving mode, comprising:

• a register module for storing mask data for each input/output device, said mask data indicating whether or not an access request signal provided by each of a plurality of input/output devices for accessing said main memory is invalidated;
• a masking module for obtaining said access request signal for each input/output device and masking said access request signal with mask data associated with said input/output device and stored in said register module;
• and
• an input module for entering a signal masked by said masking module into a processor to selectively switch the operation mode of said information processor.