Security supervisor governing allowed transactions on a system bus
AssigneeLSI Corporation
InventorsChristopher M. Giles, Simon Bewick, Kalvin E. Williams
Life of this patent
Estimating the term…
Abstract
A circuit generally comprising a plurality of master modules and a supervisor module is disclosed. The supervisor module may be configured to (i) detect a target address and a particular master module of the master modules initiating a transaction on a bus, (ii) identify a predetermined authorization in response to the particular master module, the target address and a current security mode of at least three security modes and (iii) subvert the transaction in response to the predetermined authorization restricting the transaction.
Claims20
A circuit comprising:
- a plurality of master modules each capable of being a master of a bus;
- and
- a supervisor module configured to (i) detect a target address of a transaction initiated on said bus by a particular master module of said master modules, (ii) identify a predetermined authorization of said transaction in response to (a) an identity of said particular master module, (b) said target address and (c) a current security mode of at least three security modes and (iii) subvert said transaction in response to said predetermined authorization restricting said transaction.
A method of operating a circuit, comprising the steps of:
- (A) detecting a target address of a transaction initiated on a bus by a particular master module of a plurality of master modules each capable of being a master of said bus;
- (B) identifying a predetermined authorization of said transaction in response to (i) an identity of said particular master module, (ii) said target address and (iii) a current security mode of at least three security modes;
- and
- (C) subverting said transaction in response to said predetermined authorization restricting said transaction.
A circuit comprising:
- means for detecting a target address of a transaction initiated on a bus by a particular master module of a plurality of master modules each capable of being a master on said bus;
- means for identifying a predetermined authorization of said transaction in response to (i) an identity of said particular master module, (ii) said target address and (iii) a current security mode of at least three security modes;
- and
- means for subverting said transaction in response to said predetermined authorization restricting said transaction.
Dependencies are inferred from the claim text.