Fencing off instruction buffer until re-circulation of rejected preceding and branch instructions to avoid mispredict flush

A digital processor, comprising

• an instruction fetcher to fetch a sequence of instructions, and if a branch instruction is fetched, to predict whether the branch will be taken, and accordingly select an instruction path corresponding to the prediction;
• an instruction buffer to receive instructions fetched by the instruction fetcher;
• a first execution unit to execute the branch instruction and to determine a correct instruction path;
• a second execution unit to execute a second instruction that precedes the branch instruction in the sequence of instructions;
• detection circuitry to detect a condition where the correct instruction path was not selected, the second instruction is rejected, and instructions subsequent to the branch instruction cannot be flushed;
• and
• control circuitry to prevent instructions from being received into the instruction buffer preceding the execution units when the condition is detected, until the rejected instruction is executed.

A digital system for processing data, comprising:

• a branch predictor to predict whether a branch instruction is taken and to select an instruction path corresponding to the prediction;
• a branch processing unit to execute the branch instruction to determine a correct instruction path;
• a detection unit to detect a condition where the correct instruction path was not selected, a second instruction that preceded the branch instruction is rejected, and instructions subsequent to the branch instruction cannot be flushed;
• a dispatcher to resubmit the rejected second instruction for execution;
• and
• a control unit to prevent instructions from being stored in an instruction buffer in response to the detected condition until the rejected second instruction is executed.