Multifunction hexadecimal instructions
AssigneeInternational Business Machines Corporation
InventorsEric M. Schwarz, Ronald M. Smith, Sr.
Life of this patent
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Abstract
A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.
Claims27
A method for executing a hexadecimal floating point instruction in a computer system, the computer system comprising a plurality of general registers, and a general purpose processor in communications with a computer memory, the processor comprising one or more execution units, the execution units executing instructions fetched from the computer memory, the method comprising the steps of:
- (a) fetching a hexadecimal floating point instruction;
- (b) responsive to fetching the hexadecimal floating point instruction, determining that the hexadecimal floating point instruction is either a multiply and add instruction or a multiply and subtract operation;
- and
- (c) responsive to the determining step,
- (1) fetching a first operand comprising a first exponent value and a first fraction (significand) value and a second operand comprising a second exponent value and a second fraction (significand) value;
- (2) multiplying the first fraction value and second fraction value to produce a full precision result;
- (3) fetching a third operand comprising a third exponent and a third fraction value;
- (4a) when the hexadecimal floating point instruction is a multiply and add instruction, adding the third operand to the full precision result to produce a second result;
- (4b) when the hexadecimal floating point instruction is a multiply and subtract instruction, subtracting the third operand from the full precision first, result to produce a second result;
- (5) deriving a fourth fraction value from the second result;
- and
- (6) storing a result operand, the result operand comprising the fourth fraction.
A computer program product for executing a hexadecimal floating point instruction in a computer system, the computer system comprising a plurality of general registers, and a general purpose processor in communications with a computer memory, the processor comprising one or more execution units, the execution units executing instructions fetched from the computer memory, the computer program product comprising:
- a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
- (a) fetching a hexadecimal floating point instruction;
- (b) responsive to fetching the hexadecimal floating point instruction, determining that the hexadecimal floating point instruction is either a multiply and add instruction or a multiply and subtract operation;
- and
- (c) responsive to the determining step,
- (1) fetching a first operand comprising a first exponent value and a first fraction (significand) value and a second operand comprising a second exponent value and a second fraction (significand) value;
- (2) multiplying the first fraction value and second fraction value to produce a full precision result;
- (3) fetching a third operand comprising a third exponent and a third fraction value;
- (4a) when the hexadecimal floating point instruction is a multiply and add instruction, adding the third operand to the full precision result to produce a second result;
- (4b) when the hexadecimal floating point instruction is a multiply and subtract instruction, subtracting the third operand from the full precision first result to produce a second result;
- (5) deriving a fourth fraction value from the second result;
- and
- (6) storing a result operand, the result operand comprising the fourth fraction.
A system for executing a hexadecimal floating point instruction in a computer system, the system comprising:
- a computer memory;
- a plurality of general registers, a general purpose processor in communications with the computer memory, the processor comprising one or more execution units, the execution units executing instructions fetched from the computer memory;
- wherein the computer system includes instructions to execute a method comprising the steps of:
- (a) fetching a hexadecimal floating point instruction;
- (b) responsive to fetching the hexadecimal floating point instruction, determining that the hexadecimal floating point instruction is either a multiply and add instruction or a multiply and subtract operation;
- and
- (c) responsive to the determining step,
- (1) fetching a first operand comprising a first exponent value and a first fraction (significand) value and a second operand comprising a second exponent value and a second fraction (significand) value;
- (2) multiplying the first traction value and second fraction value to produce a full precision result;
- (3) fetching a third operand comprising a third exponent and a third fraction value;
- (4a) when the hexadecimal floating point instruction is a multiply and add instruction, adding the third operand to the full precision result to produce a second result;
- (4b) when the hexadecimal floating point instruction is a multiply and subtract instruction, subtracting the third operand from the full precision first result to produce a second result;
- (5) deriving a fourth fraction value from the second result;
- and
- (b 6) storing a result operand, the result operand comprising the fourth fraction.
Dependencies are inferred from the claim text.