Testing for operating life of a memory device with address cycling using a gray code sequence
AssigneeAdvanced Micro Devices, Inc.
InventorsWan Yen Teoh, Che Seong Law
Life of this patent
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Abstract
In a method and system for cycling through addresses of a memory device, a respective bit pattern comprised of a predetermined number of bits is generated for each address. The respective bit pattern for each of the addresses is cycled through with a transition of less than the predetermined number of bits for sequencing to each subsequent address. For example, the respective bit pattern for each of the addresses is cycled through in a gray code sequence. By limiting the number of transitions in the address bits, charge gain failure of a flash memory device is minimized and even may be eliminated.
Claims20
A method of testing a memory device for determining operating life with stressing, comprising:
- cycling through each address of the memory device by generating a respective bit pattern comprised of a predetermined number of bits including row and column address bits for each address;
- applying stressing signals on a respective at least one cell of the memory device corresponding to each generated address in the cycling;
- wherein each of all possible row and column addresses of all of the row and column address bits is cycled through for application of the stressing signals;
- performing the cycling and the applying of the stressing signals for a predetermined stress time period;
- and
- minimizing charge gain failure in the memory device after the predetermined stress time period with a transition of less than the predetermined number of bits for sequencing to each subsequent address during the cycling through each of all possible row and column addresses of all of the row and column address bits.
A system for testing a memory device for determining operating life with stressing, comprising:
- an address generator for cycling through each address by generating a respective bit pattern comprised of a predetermined number of bits including row and column address bits for each address;
- signal generators for generating stressing signals applied on a respective at least one cell of the memory device corresponding to each generated address in the cycling;
- wherein each of all possible row and column addresses of all of the row and column address bits is cycled through for application of the stressing signals;
- and wherein the cycling and the applying of the stressing signals are performed for a predetermined stress time period;
- and
- means for minimizing charge gain failure in the memory device after the predetermined stress time period with a transition of less than the predetermined number of bits for sequencing to each subsequent address during the cycling through each of all possible row and column addresses of all of the row and column address bits.
Dependencies are inferred from the claim text.