US 7,254,688 B2Granted

Data processing apparatus that shares a single semiconductor memory circuit among multiple data processing units

AssigneeNEC Electronics Corporation

InventorMasakatsu Uneme

Life of this patent

Estimating the term…

Loading patent…

Abstract

Multiple data processing circuits may share a semiconductor memory circuit, such as double-data-rate synchronous dynamic random access memory (DDR-SDRAM). A data processing circuit (202-1 or 202-2) ending control of a semiconductor memory circuit (201) supplies a clock enable signal and chip select signal at predetermined levels. A data processing circuit (202-2 or 202-1) starting control of a semiconductor memory circuit (201) supplies a clock enable signal and chip select signal at the same predetermined levels, before the data processing circuit (202-1 or 202-2) ending control stops supplying a clock enable signal and chip select signal. Therefore, a clock enable signal and chip select signal do not enter an undefined state, and malfunctions that could otherwise occur are prevented.

Claims12

Dependent claims

A data processing apparatus that arbitrates sharing of a single semiconductor memory circuit among multiple data processing circuits, comprising:

a semiconductor memory circuit that executes operations corresponding to a command signal, address signal and clock signal received external to the semiconductor memory circuit, the semiconductor memory circuit includes a clock enable signal input, and a chip select signal input;
and
a data processing circuit that supplies the semiconductor memory circuit with a first clock enable signal output to the clock enable signal input for enabling an input of the clock signal when active and disabling the input of the clock signal when inactive, and a first chip select signal output to the chip select signal input for enabling input of command signals when the chip select signal is active and disabling input of command signals when the chip select signal is inactive;
wherein
before the data processing circuit ends control of the semiconductor memory circuit and stops supplying the first clock enable signal output and first chip select signal output, a different data processing circuit starting control of the semiconductor memory circuit supplies the semiconductor memory circuit with a second clock enable signal output to the clock enable signal input and a second chip enable signal output to the chip enable signal input, the second clock enable signal output and the second chip enable signal output having clock enable signal and chip select signal logic values at the same state as the first clock enable signal output and the first chip enable signal output provided by the data processing circuit ending control of the semiconductor memory circuit.

2 more elements

A data processing apparatus, comprising:

a semiconductor memory circuit that is controlled by control signal inputs to at least one control input;
at least one control line coupled to the at least one control input of the semiconductor memory circuit;
and
a plurality of data processing circuits that share access to the semiconductor memory circuit, each data processing circuit having a control output coupled to the at least one control line;
wherein
when one data processing circuit ends control of the semiconductor memory circuit, the data processing circuit provides a control signal at the control output at a predetermined potential for a first time period before ending the control signal;
and
subsequently, when another data processing circuit starts control of the semiconductor memory circuit, the another data processing circuit provides a control signal at its control output at the predetermined potential within the first time period
wherein each of the plurality of data processing curcuits includes
a request input/output (I/O) for indicating when the data processing circuit seeks control of the semiconductor memory circuit,
a grant I/O for indicating when the data processing circuit is granted control of the semiconductor memory circuit,
a busy I/O for indicating when the data processing circuit is controlling the semiconductor memory circuit,
a first switch for selectively connecting the request I/O, grant I/O, and busy I/O to a requesting circuit that generates a request indication and busy indication for the data processing circuit, and
a second switch for selectively connecting the request I/O, grant I/O, and busy I/O to an arbitration circuit that generates a grant indication;
wherein
the first switch is disabled and the second switch is enabled when the data processing circuit is initialized as a master device, and the first switch is enabled and the second switch is disabled when the data processing circuit is initialized as a slave device.

13 more elements

Dependencies are inferred from the claim text.