Semiconductor integrated circuit and data processing system

A semiconductor device comprising:

• a memory cell array having a plurality of word lines, a plurality of bit lines across the plurality of word lines, and a plurality of memory cells provided at intersections of the plurality of word lines and the plurality of bit lines;
• a plurality of sense amplifiers connected to the plurality of bit lines;
• and
• a plurality of column switches connected to the plurality of bit lines,
• wherein in a first mode, all memory cells connected to a first word line included in the plurality of word lines are written with data during activation of the first word line,
• wherein in a second mode, a predetermined number of memory cells connected to the first word line are written with data during activation of the first word line,
• wherein a time from activating the first word line to activating the column switches in the first mode is shorter than that in the second mode.