Enhanced STCX design to improve subsequent load efficiency
AssigneeInternational Business Machines Corporation
InventorsGregory William Alexander, Juan Jose Arevalo, Balaram Sinharoy, Shih-Hsiung Stephen Tung
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Abstract
A method, system and computer program product for processing in a multiprocessor data processing system are disclosed. The method includes, in response to executing a load-and-reserve instruction in a processor core, the processing core sending a load-and-reserve operation for an address to a lower level cache of a memory hierarchy, invalidating data for the address in a store-through upper level cache, and placing data returned from the lower level cache into the store-through upper level cache.
Claims20
A method of processing in a multiprocessor data processing system including a memory hierarchy including a store-through upper level cache, a lower level cache and a system memory, said method comprising:
- in response to executing a load-and-reserve instruction in a processor core, wherein said load-and-reserve instruction is characterized by setting a reservation in a unit of reservation logic:
- the processing core sending a load-and-reserve operation for an address to said lower level cache of said memory hierarchy,
- invalidating data for said address in said store-through upper level cache, and
- placing data returned from said lower level cache of said memory hierarchy into said store-through upper level cache.
A processing unit, comprising:
- a store-through upper-level cache;
- a general-purpose register;
- an execution unit that executes a load-and-reserve instruction, wherein said load-and-reserve instruction is characterized by setting a reservation in a unit of reservation logic;
- a load unit that sends a load-and-reserve operation for an address to a lower level cache of a memory hierarchy, that invalidates data for said address in said store-through upper-level cache, and that places data returned from said lower-level cache of said memory hierarchy in response to said load-and-reserve operation into said store-through upper level cache.
A data processing system, comprising:
- a memory hierarchy including a store-through upper level cache, a lower level cache and a system memory;
- a general-purpose register;
- an execution unit that executes a load-and-reserve instruction, wherein said load-and-reserve instruction is characterized by setting a reservation in a unit of reservation logic;
- and
- a load unit that sends a load-and-reserve operation for an address to said lower-level cache of said memory hierarchy, that invalidates data for said address in said store-through upper-level cache, and that places data returned from said lower-level cache of said memory hierarchy in response to said load-and-reserve operation into said store-through upper level cache.
Dependencies are inferred from the claim text.