Processor cache memory as RAM for execution of boot code
AssigneeIntel Corporation
InventorsSham M. Datta, Vincent J. Zimmer, Kushagra V. Vaid, William A. Stevens, Amy Lynn Santoni
Life of this patent
Estimating the term…
Abstract
In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, and boot code is executed, with the preloaded cache RAM appearing to the executing boot code stream as a memory store.
Claims30
A method, comprising:
- setting a data block alignment for a cache to be N/X bytes when a cache as RAM (CAR) system on the cache includes an implementation a cache size N and a set associativity of up to X-way interactions;
- preloading, as part of the CAR system, at least one column of the cache as cache random access memory (RAM), wherein the cache RAM corresponds to the data block alignment;
- using a tag to prevent cache line evictions from the cache RAM;
- and
- executing a boot code stream with the cache RAM appearing to the executing boot code stream as a memory store for the executing boot code stream.
An article of manufacture, comprising a machine-accessible storage medium having stored thereon instructions that, when executed by a machine, result in the machine performing operations comprising:
- setting a data block alignment for a cache to be N/X bytes when a cache as RAM (CAR) system on the cache includes an implementation cache size N and a set associativity of up to X-way interactions;
- preloading, as part of the CAR system, at least one column of the cache as cache random access memory (RAM), wherein the cache RAM corresponds to the data block alignment;
- using a tag to prevent cache line evictions from the cache RAM;
- and
- executing a boot code stream with the cache RAM appearing to the executing boot code stream as a memory store for the executing boot code stream.
A system, comprising:
- a cache as RAM (CAR) software module that:
- sets a data block alignment for a cache to be N/X bytes when a cache as RAM (CAR) system on the cache includes an implementation cache size N and a set associativity of up to X-way interactions;
- preloads, as part of the CAR system, at least one column of the cache as cache random access memory (RAM), wherein the cache RAM corresponds to the data block alignment;
- uses a tag to prevent cache line evictions from the cache RAM;
- and
- a processor including the cache RAM for executing a boot code stream with the cache RAM appearing to the executing boot code stream as a memory store for the executing boot code stream.
Dependencies are inferred from the claim text.