Write transaction interleaving
AssigneeArm Limited
InventorsAntony John Harris, Bruce James Mathewson
Life of this patent
Estimating the term…
Abstract
A bus master 2, 4 sends write transactions to a bus slave 8 which include separate write addresses AW and write data WD. Write transaction identifiers AWID, WID are associated with these write addresses and write data. The bus slave can accept multiple write addresses such that there can be copending write transactions to the same bus slave. The bus slave uses the write transaction identifiers to correlate interleaved write data for the co-pending write transactions with their write addresses.
Claims14
Apparatus for processing data, said apparatus comprising:
- at least one bus master operable to generate write transactions;
- and
- at least one bus slave operable to receive said write transactions;
- wherein
- a write transaction includes transferring a write address from a bus master to a bus slave and separately transferring write data from said bus master to said bus slave;
- said bus slave is operable to receive a plurality of interleaved write transactions whereby the write data of a plurality of co-pending write transactions is received in a variable order, with respect to corresponding write addresses;
- a bus master interface circuit between said bus master and said bus slave is operable to generate a transaction identifier for a write transaction, said transaction identifier being transferred over a first identifier bus channel to said bus slave with said write address and separately over a second identifier bus channel to said bus slave with said write data;
- and
- said bus slave is responsive to respective transaction identifiers associated with interleaved write transactions to correlate received writes addresses with received write data.
A method of processing data, said method comprising the steps of:
- generating write transactions with at least one bus master;
- and
- receiving said write transactions with at least one bus slave;
- wherein
- a write transaction includes transferring a write address from a bus master to a bus slave and separately transferring write data from said bus master to said bus slave;
- said bus slave receiving a plurality of interleaved write transactions whereby write data of a plurality of co-pending write transactions is received in a variable order with respect to corresponding write addresses;
- a bus master interface circuit between said bus master and said bus slave generating a transaction identifier for a write transaction, said transaction identifier being transferred over a first identifier bus channel to said bus slave with said write address and separately over a second identifier bus channel to said bus slave with said write data;
- and
- said bus slave responding to respective transaction identifiers associated with interleaved write transactions to correlate received writes addresses with received write data.
Dependencies are inferred from the claim text.