Dual mode capability for system bus

A method for transferring data in a computer system, comprising:

• scanning a value into a mode register in an interface unit of a processor arrangement in the computer system, wherein the value is either a first value or a second value;
• issuing a memory read to a system bus of the computer system by the interface unit;
• receiving from the system bus by the interface unit, a completion response for the memory read, the completion response including a source identifier and data of a memory location addressed by the memory read;
• checking parity of the source identifier by the interface unit using one of a first parity check and a second parity check, the one of the parity checks selected in response to the value in the mode register;
• comparing by the interface unit, in response to a first value in the mode register, the source identifier in the completion response to a source identifier in an acknowledgement response associated with the memory read and conditioning acceptance of the data from the completion response in response to the comparison;
• and
• comparing by the interface unit, in response to a second value in the mode register, the source identifier in the completion response to a source identifier in the memory read and conditioning acceptance of the data from the completion response in response to the comparison.

An arrangement for transferring data in a computer system, comprising:

• means for setting a value in a mode register;
• means for issuing a memory read to a system bus of the computer system;
• means for receiving from the system bus, a completion response for the memory read, the completion response including a source identifier and data of a memory location addressed by the memory read;
• means, responsive to a first value in the mode register and the source identifier in the completion response being equal to a source identifier in an acknowledgement response associated with the memory read, for receiving the data from the completion response;
• and
• means, responsive to a second value in the mode register and the source identifier in the completion response being equal to a source identifier in the memory read, for receiving the data from the completion response.