Average code generation circuit

An integrated circuit comprising:

• first and second circuits for generating m-bit binary code am-1:0 and bm-1:0, respectively;
• an asynchronous circuit coupled to the first and second circuits, wherein the asynchronous circuit is configured to generate an m-bit binary code cm-1:0 representing an average of the binary codes am-1:0 and bm-1:0 generated by the first and second circuits, respectively,
• wherein individual ones of the m-bit binary codes am-1:0, bm-1:0, and cm-1:0 include at most one series of consecutive zeros and at most one series of consecutive ones;
• a plurality of subcircuits, one of which comprises:
• first and second nand gates;
• first and second nor gates;
• first and second and gates;
• first and second inverter gates;
• wherein outputs of the nor gates and the first nand gate are coupled to respective inputs of the second nand gate;
• wherein outputs of the and gates are coupled to respective inputs of the second nor gate;
• wherein outputs of the first and second inverter gates are coupled to respective first inputs of the first and second and gates, respectively;
• wherein m=8;
• wherein first and second inputs of the first nor gate are coupled to receive a0 and b0, respectively;
• wherein second and third inputs of the first and gate are coupled to receive a1 and b3, respectively;
• wherein second and third inputs of the second and gate are coupled to receive a3 and b1, respectively;
• wherein the inputs of the first and second inverters are coupled to receive a0 and b0, respectively;
• wherein first and second inputs of the first nand gate are coupled to receive a2 and b2, respectively.

An integrated circuit comprising:

• first and second circuits for generating m-bit binary codes am-1:0 and bm-1:0, respectively;
• an asynchronous circuit for generating m-bit binary code cm-1:0 in response to the asynchronous circuit receiving binary codes am-1:0 and bm-1:0;
• wherein if binary codes am-1:0 and bm-1:0 are identical to each other or if binary codes am-1:0 and bm-1:0 differ from each other by only one bit, the asynchronous circuit generates binary code cm-1:0 identical to one of the binary codes am-1:0 and bm-1:0;
• wherein if binary codes am-1:0 and bm-1:0 differ from each other by only two bits, the asynchronous circuit generates binary code cm-1:0 which is identical to a result of left shifting one of the binary codes am-1:0 and bm-1:0 by one bit with logical zero fill at the least significant bit thereof;
• wherein if binary codes am-1:0 and bm-1:0 differ from each other by three bits, the asynchronous circuit generates binary code cm-1:0 which is identical to a result of left shifting one of the binary codes am-1:0 and bm-1:0 by two bits with logical zero fill at the least significant bit thereof.

An integrated circuit comprising:

• first and second circuits for generating m-bit binary codes am-1:0 and bm-1:0, respectively;
• an asynchronous circuit coupled to the first and second circuits, wherein the asynchronous circuit is configured to generate an m-bit binary code cm-1:0 representing an average of the binary codes am-1:0 and bm-1:0 generated by the first and second circuits, respectively, and wherein the asynchronous circuit includes
• first, second, and third nand gates;
• first, second, and third nor gates;
• wherein respective outputs of the nor gates are coupled to respective inputs of the third nand gate,
• wherein respective outputs of the first and second nand gates are coupled to respective inputs of the second nor gate,
• wherein individual ones of the m-bit binary codes am-1:0, bm-1:0, and cm-1:0 include at most one series of consecutive zeros and at most one series of consecutive ones.