Method and system for testing a memory of a microprocessor

A carrier medium including program instructions which when executed by a processor implement a method comprising:

• generating a test code segment including a number of selected opcodes;
• wherein generating the test code segment includes:
• storing a set of possible opcodes in a plurality of storage locations;
• iteratively generating a pseudo-random value;
• and
• after each iteration, using the resulting pseudo-random value to select an opcode from the set of possible opcodes until a number of opcodes have been selected;
• executing the test code segment for a plurality of iterations;
• saving a first test result of the execution of the test code segment after a first iteration;
• comparing additional test results of each subsequent iteration with the first test result;
• and
• providing a failure notification in response to determining that any of the subsequent test results are different than the first test result.

A system comprising:

• a processor;
• a memory for storing program instructions executable by the processor to implement the method comprising:
• a generating a test code segment including a number of selected opcodes;
• wherein generating the test code segment includes:
• storing a set of possible opcodes in a plurality of storage locations;
• iteratively generating a pseudo-random value;
• and
• after each iteration, using the resulting pseudo-random value to select an opcode from the set of possible opcodes until a number of opcodes have been selected;
• executing the test code segment for a plurality of iterations;
• saving a first test result of the execution of the test code segment after a first iteration;
• comparing additional test results of each subsequent iteration with the first test result;
• and
• providing a failure notification in response to determining that any of the subsequent test results are different than the first test result.

A method for testing a memory of a processor, said method comprising:

• generating a test code segment including a plurality of instructions, each including a number of selected opcodes, wherein each instruction further includes a memory reference including a memory offset, wherein the memory offset corresponds to the start of a data segment in the memory that is used by the test code segment;
• wherein generating the test code segment includes:
• storing a set of possible opcodes in a plurality of storage locations:
• iteratively generating a pseudo-random value;
• and
• after each iteration, using the resulting pseudo-random value to select an opcode from the set of possible opcodes until a number of opcodes have been selected;
• executing the test code segment for a plurality of iterations, and after each iteration of the plurality of iterations adding a predetermined value to the memory offset;
• saving within the memory, the data segment as a first test result of a first portion of the plurality of iterations;
• saving the data segment as a subsequent test result after each subsequent portion of the plurality of iterations;
• comparing each subsequent test result with the first test result;
• determining whether any of the subsequent test results are different than the first test result;
• and
• providing a failure notification in response to determining that any of the subsequent test results are different than the first test result.

A carrier medium including program instructions which when executed by a processor implement a method comprising:

• generating a test code segment including a plurality of instructions, each including a number of selected opcodes, wherein each instruction further includes a memory reference including a memory offset, wherein the memory offset corresponds to the start of a data segment in the memory that is used by the test code segment;
• wherein generating the test code segment includes:
• storing a set of possible opcodes in a plurality of storage locations;
• iteratively generating a pseudo-random value;
• and
• after each iteration, using the resulting pseudo-random value to select an opcode from the set of possible opcodes until a number of opcodes have been selected;
• executing the test code segment for a plurality of iterations, and after each iteration of the plurality of iterations adding a predetermined value to the memory offset;
• saving within the memory, the data segment as a first test result of a first portion of the plurality of iterations;
• saving the data segment as a subsequent test result after each subsequent portion of the plurality of iterations;
• comparing each subsequent test result with the first test result;
• determining whether any of the subsequent test results are different than the first test result;
• and
• providing a failure notification in response to determining that any of the subsequent test results are different than the first test result.

A system comprising:

• a processor;
• a memory for storing program instructions executable by the processor to implement the method comprising:
• generating a test code segment including a plurality of instructions, each including a number of selected opcodes, wherein each instruction further includes a memory reference including a memory offset, wherein the memory offset corresponds to the start of a data segment in the memory that is used by the test code segment;
• wherein generating the test code segment includes:
• storing a set of possible opcodes in a plurality of storage locations;
• iteratively generating a pseudo-random value;
• and
• after each iteration, using the resulting pseudo-random value to select an opcode from the set of possible opcodes until a number of opcodes have been selected;
• executing the test code segment for a plurality of iterations, and after each iteration of the plurality of iterations adding a predetermined value to the memory offset;
• saving within the memory, the data segment as a first test result of a first portion of the plurality of iterations;
• saving within the memory, the data segment as a subsequent test result after each subsequent portion of the plurality of iterations;
• comparing each subsequent test result with the first test result;
• determining whether any of the subsequent test results are different than the first test result;
• and
• providing a failure notification in response to determining that any of the subsequent test results are different than the first test result.