Method and apparatus for calibrating delay lines

A tester for testing integrated circuits (ICs), the tester comprising:

• a plurality of ICs for generating test pattern waveforms, each IC for generating test pattern waveforms comprising a plurality of delay line (DL) circuits, each DL circuit comprising
• a pulse generating circuit having an input and an output, the pulse generating circuit generating an electrical pulse signal upon receiving an edge of an electrical signal, the pulse signal having a substantially fixed time duration,
• a delay line having an input and an output, the delay line comprising a plurality of delay elements and delay element selection logic, the delay line receiving at the input of the delay line a pulse signal output from the pulse generating circuit and delaying the pulse signal from arriving at the output of the delay line by a time delay of a duration that depends on selection or deselection of delay elements by the delay element selection logic,
• a feedback loop for feeding the delayed pulse signal output from the delay line back to the input of the pulse generating circuit, wherein receiving an edge of the fed back pulse signal at the input of the pulse generating circuit causes the pulse generating circuit to generate a pulse signal, and
• a counter that receives the delayed pulse signal output from the delay line and generates a counter value that is based on a period of oscillation of the delayed pulse signal;
• and
• a plurality of output pins for outputting test pattern waveforms generated by the ICs.

A method for calibrating delay lines in an integrated circuit (IC), the method comprising:

• in a pulse generating circuit, generating an electrical pulse signal having a substantially fixed time duration, the pulse generating circuit generating the pulse upon receiving an edge of an electrical signal at an input of the pulse generating circuit;
• outputting the generated pulse signal from an output of the pulse generating circuit;
• receiving at the input of the delay line the pulse signal output from the pulse generating circuit;
• delaying the pulse signal from arriving at an output of the delay line by a selected time delay;
• and
• feeding the delayed pulse signal output from the delay line back to the input of the pulse generating circuit, wherein receiving an edge of the fed back pulse signal at the input of the pulse generating circuit causes the pulse generating circuit to generate another pulse signal.