Image processor processing image data in parallel with a plurality of processors

An image processor comprising:

• a plurality of processors performing prescribed processing on a plurality of data divided from single image data respectively;
• a first memory accepting and storing arrangement information in said single image data for said plurality of divided data, said arrangement information for each of said plurality of divided data being associated with whichever processor performs the prescribed processing of the divided data;
• and
• a controller restoring a single image from said plurality of data processed in said plurality of processors in accordance with said arrangement information.

An image processing method including steps of:

• dividing input image data into a plurality of image data;
• storing information indicating arrangement of said divided image data relative to said input image;
• performing image processing on said divided image data with a plurality of processors;
• outputting said processed data as well as said information indicating arrangement of said divided data;
• and
• restoring a single image from said processed data in accordance with said information indicating arrangement of said divided data,
• wherein each of said plurality of processors processes plural portions of said divided image data, and information indicating arrangement of each divided portion of said image data is associated with whichever processor processes the corresponding divided portion.

An image processor comprising:

• first and second processors having:
• an input image data port and an input image address port, for inputting, respectively, image data corresponding to a portion of an image and a position of the image data within the image;
• and
• an output image data port and an output image address port for outputting, respectively, processed image data corresponding to a portion of a processed image and a position of said processed image data within the processed image;
• and
• a data flow control, coupled to said first and second processors, for coordinating the operation thereof so that each of said first and second processors process plural portions of said input image and said first and second processors processes said plural portions asynchronously with respect to each other.

An image processor comprising:

• a plurality of processors processing respective portions of the same input image data in parallel with each other and outputting respective processed portions of said input image data;
• and
• an address memory accepting and storing address information related to a position of each portion of said input image data within said input image data for each respective portion of image data which has been processed by said plurality of processors;
• an image memory storing said image data output from said plurality of processors, and
• a reader reading said image data from said image memory on the basis of said address information stored in said address memory.

An image processor comprising:

• a plurality of processors processing respective portions of the same input image data in parallel with each other and outputting respective processed portions of said input image data;
• and
• an address memory accepting and storing address information related to a position of each portion of said input image data within said input image data for each respective portion of image data which has been processed by said plurality of processors;
• an input unit inputting image data subjected to processing in synchronization with a first external device, and
• an output unit outputting said image data processed in said plurality of processors and said address information stored in said address memory in synchronization with a second external device.

An image processor comprising:

• a plurality of processors processing respective portions of the same input image data in parallel with each other and outputting respective processed portions of said input image data;
• and
• an address memory accepting and storing address information related to a position of each portion of said input image data within said input image data for each respective portion of image data which has been processed by said plurality of processors;
• wherein said address information is stored so that said address information is associated with whichever processor of the plurality of processors processed the portion of said input image data related to the address information.