Clock and data recovery circuit and method
AssigneeSamsung Electronics Co., Ltd.
InventorJu-Hyung Kim
Life of this patent
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Abstract
In a clock and data recovery circuit and method, the clock and data recovery circuit comprises a clock signal generator for generating N clock signals, each clock signal having phase difference of 360/N×K from each other, wherein the N denotes an integer and the K denotes an integer from 0 to N−1, a phase selector for generating an I+2th clock signal out of the N clock signals as a recovered clock signal if an Ith clock signal is on a first state and an I+1th clock signal is on a second state when logic level transition of a received data is detected, wherein the I denotes an integer from 1 to N, and a recovered data generator for generating a recovered data synchronized with the recovered clock signal by using the received data in response to the recovered clock signal output from the phase selector.
Claims6
A clock and data recovery circuit comprising:
- a clock signal generator that generates N clock signals, each clock signal having a phase difference of 360/N degrees from each other, wherein N denotes an integer, and wherein phases of the N clock signals are 360/N×K, wherein K denotes an integer from K=0 to N−1;
- a phase selector that selects an (I+2)th clock signal of the N clock signals as a recovered clock signal if an clock signal of the N clock signals is in a first state and if an (I+1)th clock signal of the N clock signals is in a second state when a logic level transition of a received data is detected, wherein I denotes an integer from 1 to N;
- and
- a recovered data generator that receives the received data and the recovered clock signal to generate a recovered data that is synchronized with the recovered clock signal output from the phase selector.
A method for recovering clock and data information from a signal comprising:
- generating a plurality of clock signals, each clock signal having a phase difference of 360/N degrees from each other, wherein N denotes an integer, and wherein phases of the N clock signals are 360/N×K, wherein K denotes an integer from K=0 to N−1;
- selecting an (I+2)th clock signal of the N clock signals as a recovered clock signal if an Ith clock signal of the N clock signals is in a first state and if an (I+1)th clock signal of the N clock signals is in a second state when a logic level transition of a received data is detected, wherein I denotes an integer from 1 to N;
- and
- receiving the received data and the recovered clock signal to generate the recovered data that is synchronized with the recovered clock signal.
Dependencies are inferred from the claim text.