Digitally adjusted high speed analog equalizer
AssigneeApplied Micro Circuits Corporation
InventorsWei Fu, Joseph James Balardeta
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Abstract
A high speed CMOS-implemented equalizer architecture as described herein utilizes a digitally controlled analog equalization scheme to equalize intersymbol interference present in an input signal. The equalizer structure includes an inductor high frequency gain boosting stage and a feed forward high frequency equalizer stage connected in series. The equalization performed by each of these gain boosting stages is controlled by one or more digital control signals. The combination of these stages results in the equalization of both amplitude and phase distortion. The equalizer architecture is suitable for use with communication systems that operate at 11.2 Gbps speeds.
Claims20
An equalizer circuit comprising:
- an inductor gain amplifier configured to provide high frequency gain boosting to amplify an input signal into an equalized signal;
- a resistor gain amplifier configured to amplify said input signal into an amplified signal;
- a summer connected to receive said equalized signal and said amplified signal, and to generate an output signal representing a weighted sum of said equalized signal and said amplified signal;
- and
- a digital-to-analog converter (“DAC”) connected to said summer, said DAC being configured to receive a digital control signal and to convert said digital control signal into at least one analog control signal utilized by said summer, wherein weighting of said equalized signal and said amplified signal is responsive to said at least one analog control signal.
An equalizer circuit comprising:
- a resistor gain amplifier configured to amplify an input signal into an amplified signal;
- a subtractor connected to receive said amplified signal and said input signal, and to generate an output signal representing a weighted difference of said amplified signal and said input signal;
- and
- a digital-to-analog converter (“DAC”) connected to said subtractor, said DAC being configured to receive a digital control signal and to convert said digital control signal into at least one analog control signal utilized by said subtractor, wherein weighting of said amplified signal and said input signal is responsive to said at least one analog control signal.
An equalizer circuit comprising:
- an input amplifier stage configured to amplify an input signal into a first intermediate signal;
- an inductor gain boosting stage connected to receive said first intermediate signal, said inductor gain boosting stage being configured to provide high frequency gain boosting to said first intermediate signal, in response to a first digital control signal, resulting in a second intermediate signal;
- and
- a feed forward equalizer stage connected to receive said second intermediate signal, said feed forward equalizer stage being configured to provide high frequency gain boosting and phase distortion correction to said second intermediate signal, in response to a second digital control signal, resulting in an output signal.
A method for equalizing a data signal in a communication system, said method comprising:
- receiving an input data signal;
- equalizing said input data signal, with an equalizer circuit having an inductor gain boosting stage in series with a feed forward equalizer stage, to produce an equalized output data signal;
- measuring an error metric associated with said equalized output data signal;
- generating at least one digital control signal in response to said error metric;
- and
- adjusting said equalizer circuit in response to said at least one digital control signal.
Dependencies are inferred from the claim text.