Semiconductor memory device

A semiconductor memory device having a burst read operation function, comprising:

• an internal address generating circuit sequentially generating internal addresses in a burst read operation, with an external address being set as an initial value;
• a memory core having a plurality of memory cells, and sequentially outputting data in the burst read operation in response to activation of a column selection signal, the data being read from the memory cells corresponding to the internal addresses;
• and
• a memory core control circuit having:
• a column control circuit repeating an operation of activating said column selection signal for a certain period of time during an activation period of an external control signal in the burst read operation, and forcibly deactivating said column selection signal in synchronization with deactivation of the external control signal, the external control signal being for instructing start/end of the burst read operation;
• and
• an operation state control circuit deactivating an operation state control signal in the burst read operation after a predetermined time has elapsed from the deactivation of said external control signal, the operation state control signal being for instructing activation/deactivation of said memory core.