Semiconductor memory device
AssigneeNEC Electronics Corporation
InventorsHiroshi Sugawara, Kazuo Watanabe
Life of this patent
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Abstract
A semiconductor memory device has: a word driver configured to apply a driving voltage to a word line connected to a memory cell; and an internal power supply circuit configured to supply the driving voltage to the word driver and to apply a substrate voltage to back gates of transistors included in the word driver. The internal power supply circuit controls the driving voltage and the substrate voltage independently of each other. In a read operation, the internal power supply circuit constantly supplies the substrate voltage, while turns on and off supply of the driving voltage.
Claims15
A semiconductor memory device comprising:
- a word driver configured to apply a driving voltage to a word line connected to a memory cell;
- and
- an internal power supply circuit configured to supply said driving voltage to said word driver and to apply a substrate voltage to back gates of transistors included in said word driver,
- wherein said internal power supply circuit controls said driving voltage and said substrate voltage independently of each other, and
- wherein in a read operation, said internal power supply circuit constantly supplies said substrate voltage, while turning on and off supply of said driving voltage.
A semiconductor memory device comprising:
- a word driver configured to apply a driving voltage to a word line connected to a memory cell;
- and
- an internal power supply circuit configured to supply said driving voltage to said word driver and to apply a substrate voltage to back gates of transistors included in said word driver,
- wherein said internal power supply circuit controls said driving voltage and said substrate voltage independently of each other, and
- wherein said word driver includes a level shifter, and said transistors include a P-channel transistor of said level shifter.
A semiconductor memory device comprising:
- a word driver configured to apply a driving voltage to a word line connected to a memory cell;
- and
- an internal power supply circuit configured to supply said driving voltage to said word driver and to apply a substrate voltage to back gates of transistors included in said word driver,
- wherein said internal power supply circuit controls said driving voltage and said substrate voltage independently of each other, and
- wherein said internal power supply circuit comprises:
- a first power supply switch connected to said word driver through a first power supply interconnection;
- and
- a second power supply switch connected to said word driver through a second power supply interconnection,
- wherein said first power supply switch constantly supplies said substrate voltage to said first power supply interconnection, and said second power supply switch supplies said driving voltage to said second power supply interconnection in response to a select signal.
A semiconductor memory device comprising:
- a word line connected to a memory cell;
- and
- a word driver having a first transistor and a second transistor configured to drive said word line,
- wherein said first transistor has a back gate to which a first voltage is applied before a read address transition, said first voltage being also applied to said word line when said word line is selected in a read operation, and
- wherein said second transistor has a back gate to which a second voltage is applied before said read address transition, said second voltage being also applied to said word line when said word line is unselected in said read operation.
Dependencies are inferred from the claim text.