Circuit and method for high speed sensing
AssigneeMacronix International Co., Ltd.
InventorsChun-Hsiung Hung, Su-Chueh Lo, Shou Wei Huang
Life of this patent
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Abstract
A circuit and method for sensing a difference between a first signal, such as a signal from the source side of a memory cell, and a second signal, such as a signal from a reference dummy cell, includes developing first and second voltages respectively in response to the first and second signals, determining the time at which the second voltage developed in response to the second signal reaches a threshold level above a latch switching point, and latching a state of the first voltage and second voltage at the determined time using a latch circuit. The threshold level above the latch switching point is set so that potential mismatch in the components of the latch circuit is overcome prior to latching.
Claims20
A method for sensing a difference between a first signal and a second signal, comprising:
- developing first and second voltages in response to the first and second signals;
- and
- latching a state of the first and second voltages in a latch circuit, responsive to the second voltage reaching a threshold level above a latch switching point of the latch circuit.
An integrated circuit including one or more sense amplifiers, the one or more sense amplifiers sensing a difference across respective first and second signal terminals, the sense amplifier comprising:
- a latch circuit, having a first input and a second input and a latch switching point, and having a sense enable input, which captures a state of the first and second inputs in response to a sense timing signal on the sense enable input;
- a first current source;
- a second current source;
- an input stage coupled to the first and second signal terminals, and having outputs coupled to the first input and the second input of the latch circuit, the input stage developing a voltage on the first input in response to a signal on the first signal terminal, and a voltage on the second input in response to a signal on the second signal terminal, the input stage including:
- a first integrator including:
- a first current control circuit having an input node coupled to the first current source, a control node coupled to the first signal terminal, and an output node coupled to the first input of the latch circuit;
- and
- a first circuit having an output node coupled to the first input of the latch circuit, a control node coupled to a reference voltage, and an input node coupled to a ground reference;
- and
- a second integrator including:
- a second current control circuit, having an input node coupled to the second current source, a control node coupled to the second signal terminal, and an output node coupled to the second input of the latch circuit;
- and
- a second circuit, having an output node coupled to the second input of the latch circuit, a control node coupled to the reference voltage, and an input node coupled to the ground reference;
- and
- a source for the sense timing signal coupled to the sense enable input, causing the latch circuit to latch the state of the first and second inputs after the voltage developed on one of the first and second inputs reaches a threshold level above the latch switching point.
Dependencies are inferred from the claim text.