Semiconductor memory device for improving response margin of redundancy flag signal and redundancy driving method for the same

A flash memory device adapted for use in a burst mode operation, comprising:

• a normal cell array comprising a plurality of NAND-type non-volatile memory cells arranged in a matrix of rows and columns;
• a redundant cell array comprising a plurality of NAND-type non-volatile memory cells adapted to replace the NAND-type non-volatile memory cells of the normal cell array;
• an address input unit adapted to generate an internal address that sequentially changes in response to a counted signal and in accordance with a burst value defining the burst operation;
• an address decoding unit adapted to decode the internal address to specify a memory cell in the normal cell array;
• a redundancy enable unit adapted to generate a redundancy shift signal in response to the generation of an internal address corresponding to a predetermined embedded address;
• and
• a data input/output unit controlled such that data from the redundant cell array, instead of the normal cell array, is output in response to the redundancy shift signal;
• wherein the embedded address corresponds to an internal address preceding the internal address specifying a memory cell in the normal cell array to be repaired by a number of shift clocks, wherein the number of shift clocks is defined by an integer equal to or greater than 1.

A redundancy driving method for a semiconductor memory device comprising a normal cell array and a redundancy cell array, comprising:

• generating a sequentially changing internal address that specifies a memory cell in the normal cell array in response to a counted signal;
• sensing generation of an internal address corresponding to an embedded address, activating a redundancy flag signal, and in response generating a redundancy shift signal from the redundancy flag signal;
• and
• controlling a data input operation such that input data is applied to the redundant cell array instead of the normal cell array in response to the redundancy shift signal;
• wherein the embedded address corresponds to an internal address preceding the internal address specifying a memory cell in the normal cell array to be repaired by a number of shift clocks, wherein the number of shift clocks is defined by an integer equal to or greater than 1.

A redundancy driving method for a semiconductor memory device comprising a normal cell array and a redundancy cell array, comprising:

• generating a sequentially changing internal address that specifies a memory cell in the normal cell array in response to a counted signal;
• sensing generation of an internal address corresponding to an embedded address, activating a redundancy flag signal, and in response generating a redundancy shift signal from the redundancy flag signal;
• and
• controlling a data output operation such that output data is received from the redundant cell array instead of the normal cell array in response to the redundancy shift signal;
• wherein the embedded address corresponds to an internal address preceding the internal address specifying a memory cell in the normal cell array to be repaired by a number of shift clocks, wherein the number of shift clocks is defined by an integer equal to or greater than 1.