Integrated circuit memory system having dynamic memory bank count and page size

A memory system comprising:

• a master device;
• and
• an integrated circuit memory device, including:
• a storage array having a first and second row of storage cells;
• and
• a row of sense amplifiers including a first plurality of sense amplifiers and a second plurality of sense amplifiers, coupled to the storage array, to access the first and second rows of storage cells, wherein the integrated circuit memory device is operable in a first mode and second mode of operation, wherein:
• during the first mode of operation, the integrated circuit memory device has a first bank count and a first page size, a first plurality of data is transferred from the first row of storage cells to the row of sense amplifiers, and
• during the second mode of operation, the integrated circuit memory device has a second bank count and a second page size, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers, and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers, wherein the second bank count is greater than the first bank count and the first page size is larger than the second page size.

An integrated circuit memory device, comprising:

• a memory bank having a first and second row of storage cells;
• and
• means for transferring data to a plurality of sense amplifiers, including:
• means for transferring in a first operation mode, while providing a first number of memory banks and a first page size, a first plurality of data from the first row of storage cells in the memory bank to a first plurality of sense amplifiers in the plurality of sense amplifiers;
• and
• means for transferring in a second operation mode, while providing a second number of memory banks and a second page size, a second plurality of data from the first row of storage cells in the first memory bank to the first plurality of sense amplifiers in the plurality of sense amplifiers and simultaneously transferring a third plurality of data from the second row of storage cells in the first memory bank to a second plurality of sense amplifiers in the plurality of sense amplifiers, wherein the second number of memory banks is greater than the first number of memory banks and the first page size is larger than the second page size.