Back to results
US 7,254,074 B2Granted
Open digit line array architecture for a memory array
AssigneeMicron Technology, Inc.
InventorsSei Seung Yoon, Charles L. Ingalls, David Pinney, Howard C. Kirsch
Life of this patent
Estimating the term…
Abstract
A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.
Claims34
An open digit line array architecture, comprising:
- a first plurality of sense of amplifiers, each sense amplifier of the first plurality coupled to a respective pair of digit lines;
- a second plurality of sense amplifiers, each sense amplifier of the second plurality coupled to a respective pair of digit lines, the second plurality of sense amplifiers having at least a first group of sense amplifiers and a second group of sense amplifiers, the first and second groups of sense amplifiers independently couplable to a power supply;
- a common reference line;
- a first plurality of switches coupled to a respective first digit line of the pair of digit lines coupled to the first plurality of sense amplifiers and further coupled to the common reference line, each switch configured to selectively couple the respective first digit line to the common reference line;
- and
- a second plurality of switches coupled to a respective first digit line of the pair of digit lines coupled to the second plurality of sense amplifiers and further coupled to the common reference line, the second plurality of switches having at least first and second groups of switches, the first group of switches coupled to the first digit lines of the pairs of digit lines coupled to the first group of sense amplifiers and configured to selectively couple the respective first digit lines to the common reference line, the second group of switches coupled to the first digit lines of the pairs of digit lines coupled to the second group of sense amplifiers and configured to selectively couple the respective first digit lines to the common reference line, the first and second groups of switches independently activatable to independently couple the first digit lines of the respective group of sense amplifiers to the common reference line.
3 more elements
A memory device, comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- a memory-cell array coupled to the address decoder, control circuit, and read/write circuit, the memory-cell array having an open digit line array architecture, the open digit line array architecture, comprising:
- a first plurality of sense of amplifiers, each sense amplifier of the first plurality coupled to a respective pair of digit lines;
- a second plurality of sense amplifiers, each sense amplifier of the second plurality coupled to a respective pair of digit lines, the second plurality of sense amplifiers having at least a first group of sense amplifiers and a second group of sense amplifiers, the first and second groups of sense amplifiers independently couplable to a power supply;
- a common reference line;
- a first plurality of switches coupled to a respective first digit line of the pair of digit lines coupled to the first plurality of sense amplifiers and further coupled to the common reference line, each switch configured to selectively couple the respective first digit line to the common reference line;
- and
- a second plurality of switches coupled to a respective first digit line of the pair of digit lines coupled to the second plurality of sense amplifiers and further coupled to the common reference line, the second plurality of switches having at least first and second groups of switches, the first group of switches coupled to the first digit lines of the pairs of digit lines coupled to the first group of sense amplifiers and configured to selectively couple the respective first digit lines to the common reference line, the second group of switches coupled to the first digit lines of the pairs of digit lines coupled to the second group of sense amplifiers and configured to selectively couple the respective first digit lines to the common reference line, the first and second groups of switches independently activatable to independently couple the first digit lines of the respective group of sense amplifiers to the common reference line.
10 more elements
A computer processing system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and output devices;
- and
- a memory device, comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- and
- a memory-cell array coupled to the address decoder, control circuit, and read/write circuit, the memory-cell array having an open digit line array architecture, the open digit line array architecture, comprising:
- a first plurality of sense of amplifiers, each sense amplifier of the first plurality coupled to a respective pair of digit lines;
- a second plurality of sense amplifiers, each sense amplifier of the second plurality coupled to a respective pair of digit lines, the second plurality of sense amplifiers having at least a first group of sense amplifiers and a second group of sense amplifiers, the first and second groups of sense amplifiers independently couplable to a power supply;
- a common reference line;
- a first plurality of switches coupled to a respective first digit line of the pair of digit lines coupled to the first plurality of sense amplifiers and further coupled to the common reference line, each switch configured to selectively couple the respective first digit line to the common reference line;
- and
- a second plurality of switches coupled to a respective first digit line of the pair of digit lines coupled to the second plurality of sense amplifiers and further coupled to the common reference line, the second plurality of switches having at least first and second groups of switches, the first group of switches coupled to the first digit lines of the pairs of digit lines coupled to the first group of sense amplifiers and configured to selectively couple the respective first digit lines to the common reference line, the second group of switches coupled to the first digit lines of the pairs of digit lines coupled to the second group of sense amplifiers and configured to selectively couple the respective first digit lines to the common reference line, the first and second groups of switches independently activatable to independently couple the first digit lines of the respective group of sense amplifiers to the common reference line.
16 more elements
A method of sensing a respective data state of a plurality of memory cells, comprising:
- precharging a first plurality of digit lines to a precharge voltage level;
- precharging a second plurality of digit lines to a precharge voltage level;
- driving each digit line of a third plurality of digit lines to a voltage level;
- coupling the plurality of memory cells to a respective one of the first plurality of digit lines;
- coupling the second plurality of digit lines to the third plurality of digit lines to provide a reference voltage;
- latching a data state for each memory cell of the plurality based on a respective voltage differential between each digit line of the first plurality and a respective digit line of the second plurality.
3 more elements
Dependencies are inferred from the claim text.