Memory device having an array of resistive memory cells
AssigneeInfineon Technologies AG
InventorThomas Röhr
Life of this patent
Estimating the term…
Abstract
A memory device including an array of resistive memory cells, which are arranged in columns and rows, and wherein each resistive memory cell each is connected to a word line, to a bit line, and to a reference electrode. The word lines are assigned to the rows and the bit lines are assigned to the columns. The resistive state of the resistive memory cells corresponds to a logical state thereof, and the memory device further comprises an evaluation device, which is coupled to the bit lines, for evaluating the resistive state of at least one of the resistive memory cells during a reading operation. The respective resistive memory cell is selected by addressing the word line to which the resistive memory cell is connected.
Claims26
A memory device, comprising:
- an array of resistive memory cells, the resistive memory cells being arranged in columns and rows,
- the resistive memory cells each being connected to a word line, to a bit line, and to a reference electrode, the word lines being assigned to the rows and the bit lines being assigned to the columns,
- wherein a resistive state of the resistive memory cells corresponds to a logical state of the resistive memory cells;
- an evaluation device coupled to the bit lines for evaluating the resistive state of at least one of the resistive memory cells during a reading operation, the respective resistive memory cell being selected by addressing the word line to which the resistive memory cell is connected;
- and
- a charging device coupled to the bit lines, the charging device charging the bit lines to a pre-determined pre-reading bit line potential before carrying out a reading operation, the charging device comprising a further row of resistive memory cells, each memory cell being connected to a respective bit line.
A memory device, comprising:
- an array of resistive memory cells, the resistive memory cells being arranged in columns and rows,
- the resistive memory cells each being connected to a word line, to a bit line, and to a reference electrode, said word lines being assigned to the rows and said bit lines being assigned to the columns,
- wherein a resistive state of the resistive memory cells corresponds to a logical state of the resistive memory cells;
- an evaluation device coupled to the bit lines for evaluating the resistive state of at least one of the resistive memory cells during a reading operation, the respective resistive memory cell being selected by addressing the word line to which the resistive memory cell is connected;
- a multiplexing device coupled to at least two bit lines to connect one of the bit lines to the evaluation device;
- and
- a charging device coupled to the bit lines, the charging device charging the bit lines to a pre-determined pre-reading bit line potential before carrying out a reading operation, the charging device comprising a further row of resistive memory cells, each memory cell being connected to a respective bit line.
Dependencies are inferred from the claim text.