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US 7,254,072 B2Granted
Semiconductor memory device having hierarchically structured data lines and precharging means
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorNaoki Kuroda
Life of this patent
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Abstract
A semiconductor memory device is provided comprising precharge circuits corresponding to global data line pairs, but not a precharge circuit corresponding to a local data line pair. In a command waiting state, data line selection switches are controlled to be in a connected state, so that the local data line pair and the global data line pairs are precharged all together while being connected to each other. In a command executing state, one of the data line selection switches, the one being not required for command execution, is in an open state. Similarly, a semiconductor memory device comprising only a precharge circuit corresponding to a local data line pair can be provided.
Claims6
A semiconductor memory device having hierarchically structured data lines, comprising:
- a plurality of memory cells disposed in a first direction and a second direction perpendicular to each other;
- a plurality of word lines disposed in the first direction and used for selecting the memory cells disposed in the second direction simultaneously;
- a plurality of bit line pairs disposed in the second direction, and connected to and shared by the memory cells disposed in the first direction;
- a plurality of sense amplifiers for amplifying signals on the bit line pairs;
- a write circuit for writing externally input data into the memory cell;
- a read circuit for outputting data read from the memory cell to an outside;
- a plurality of global data line pairs each provided corresponding to one or more of the bit line pairs;
- a local data line pair provided corresponding to two or more of the global data line pairs and connected to the write circuit and the read circuit;
- a plurality of data line selection switches provided corresponding to the global data line pairs and used for switching states of connection between the global data line pairs and the local data line pair;
- and
- a plurality of precharge circuits provided corresponding to the global data line pairs and operated in accordance with a received control signal,
- wherein, in a command waiting state, all of the data line selection switches are in a connected state and all of the precharge circuits are operated, and
- wherein, if a command state is transitioned from the command waiting state, in which precharge processing is performed, to a command executing state, in which write processing or read processing is performed, one of the plurality of data line selection switches, which is required for command execution, is held in the connected state while the remainder of the plurality of data line selection switches are transitioned from being in the connected state to being in an open state, and operations of all of the precharge circuits are stopped.
10 more elements
A semiconductor memory device having hierarchically structured data lines, comprising:
- a plurality of memory cells disposed in a first direction and a second direction perpendicular to each other;
- a plurality of word lines disposed in the first direction and used for selecting the memory cells disposed in the second direction simultaneously;
- a plurality of bit line pairs disposed in the second direction, and connected to and shared by the memory cells disposed in the first direction;
- a plurality of sense amplifiers for amplifying signals on the bit line pairs;
- a write circuit for writing externally input data into the memory cell;
- a read circuit for outputting data read from the memory cell to an outside;
- a plurality of global data line pairs each provided corresponding to one or more of the bit line pairs;
- a local data line pair provided corresponding to two or more of the global data line pairs and connected to the write circuit and the read circuit;
- a plurality of data line selection switches provided corresponding to the global data line pairs and used for switching states of connection between the global data line pairs and the local data line pair;
- and
- a plurality of precharge circuits provided corresponding to the global data line pairs and operated in accordance with a received control signal,
- wherein, in a command waiting state, all of the data line selection switches are in a connected state and all of the precharge circuits are operated, and
- wherein, if a command state is transitioned from the command waiting state, in which precharge processing is performed, to a command executing state, in which write processing or read processing is performed, one of the plurality data line selection switches, which is required for command execution, is held in a connected state while the remainder of the plurality of data line selection switches are transitioned from being in the connected state to being in an open state, and an operation of one of the plurality of precharge circuits corresponding to the global data line pairs, which is required for the command execution, is stopped while operations of the remainder of the plurality of precharge circuits are continued.
10 more elements
Dependencies are inferred from the claim text.