Semiconductor memory device storing redundant replacement information with small occupation area
AssigneeRenesas Technology Corp.
InventorsMasaru Haraguchi, Takeshi Fujino
Life of this patent
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Abstract
Column redundancy data storage circuit blocks storing column redundancy data for repairing defective columns are arranged in correspondence to respective memory cell array blocks. The storage data of the column redundancy data storage circuits is transferred to redundancy data hold circuits arranged in spare column decoder bands adjacent to the data paths for transferring internal data, and are decoded for selection of a page in the spare decoder bands during column access. Therefore, it is possible to reduce the occupation area of a fuse program circuit which programs redundancy data for repairing a defective column.
Claims20
A semiconductor memory device comprising:
- a plurality of memory array blocks, each having a plurality of memory cells arranged in rows and columns;
- a plurality of redundancy data storage circuits, distributedly arranged, corresponding to and along regions having corresponding memory array blocks placed thereon, each data storage circuit individually storing redundancy data specifying a defective column of a corresponding memory array block;
- and
- a plurality of row decoder circuits arranged in correspondence with the memory array blocks and on an opposite side of the corresponding memory array blocks from the corresponding redundancy data storage circuits for the corresponding memory array blocks, each row decoder circuit decoding a received address signal to select an addressed row in the corresponding memory array block.
A semiconductor memory device comprising:
- a plurality of memory array blocks, each memory block having a plurality of memory cells arranged in rows and columns;
- a plurality of redundancy data storage circuits, arranged physically in correspondence with the memory array blocks, each redundancy data storage circuit individually storing redundancy data specifying a defective row and a defective column of a corresponding memory array block;
- a plurality of redundancy data hold circuits, arranged physically in correspondence with the memory array blocks, each redundancy data hold circuit individually holding redundancy data of the defective row and the defective column of the corresponding memory array block;
- a redundancy transfer circuit for transferring redundancy data between the redundancy data storage circuits and the redundancy data hold circuits;
- a transfer control circuit for controlling transfer operation of the redundancy transfer circuit in initialization of internal circuitry;
- and
- a plurality of row decoder circuits arranged in correspondence with the memory array blocks and on an opposite side of the corresponding memory array blocks from the corresponding redundancy data storage circuits for the corresponding memory array blocks, each row decoder circuit selecting a row in a corresponding memory array block, in accordance with an applied address signal and defective row address information stored in a corresponding redundancy data hold circuit.
Dependencies are inferred from the claim text.