US 7,254,067 B2 · Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency

Abstract

A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. The logic circuit maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active.

Claims16

Dependent claims

In a memory device having a plurality of write receivers to which respective write data bits may be applied from a plurality of respective data bus terminals and a plurality of read transmitters that may apply respective read data bits to the respective data bus terminals, a method of operating the write receivers in either a first mode or a second mode, the method comprising:

applying power to the write receivers regardless of whether the write data bits are being applied to the write receivers when the read transmitters are not active when the write receivers are being operated in the first mode;
removing power from the write receivers when the read transmitters are active when the write receivers are being operated in the first mode;
applying power to the write receivers when the write data bits are being applied to the write receivers when the write receivers are being operated in the second mode;
and
removing power to the write receivers when either the write data bits are not being applied to the write receivers or the read transmitters are active when the write receivers are being operated in the second mode.

2 more elements

Dependencies are inferred from the claim text.

Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency

Life of this patent

Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency

Life of this patent

Abstract

Claims16