Non-volatile semiconductor memory device and method for reading the same
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorToshiki Mori
Life of this patent
Estimating the term…
Abstract
In a reference cell 202, first and second cells 50 and 52 having the same structure as that of a memory cell are provided. A memory cell current IREF1 of the first cell 50 is set to be a minimum value of a memory cell current after an erase operation. A memory cell current IREF2 of the second cell 52 is set to be a maximum value of a memory cell current after a write operation. The read circuit 206 compares a memory cell current Icell with a current (IREF1+IREF2)/2 and outputs a comparison result. A current source for use in erase verification and write verification may be used in place of the first and second cells 50 and 52.
Claims21
A method for reading data, in a non-volatile semiconductor memory device comprising a plurality of memory cells, from the memory cell set in one of at least two states, the method comprising the steps of:
- obtaining a read current of the memory cell to be read as a first current;
- obtaining a second current based on a first verification reference current used for erase verification of the memory cell and a second verification reference current used for write verification of the memory cell;
- and
- calculating data stored in the memory cell to be read, depending on whether the first current is larger than, smaller than, or equal to the second current.
A circuit for reading data from a non-volatile semiconductor memory device comprising a plurality of memory cells, the circuit comprising:
- a first current generation circuit of generating a first verification reference current used for erase verification of the memory cell;
- a second current generation circuit of generating a second verification reference current used for write verification of the memory cell;
- a first current supply circuit of supplying a read current as a first current to the memory cell to be read;
- a second current supply circuit of supplying a second current based on the first verification reference current and the second verification reference current;
- and
- a comparison section of calculating data stored in the memory cell to be read, depending on whether the first current is larger than, smaller than, or equal to the second current.
A method for reading data, in a non-volatile semiconductor memory device comprising a plurality of memory cells and a plurality of reference cells, from the memory cell set in one of at least two states, wherein
- a first reference cell is set so that a read current thereof coincides with a maximum or minimum value of a read current of the memory cell set in a first state, and
- a second reference cell is set so that a read current thereof coincides with a maximum or minimum value of a read current of the memory cell set in a second state,
- the method comprising the steps of:
- obtaining a read current of the memory cell to be read as a first current;
- obtaining a second current based on the read current of the first reference cell and the read current of the second reference cell;
- and
- calculating data stored in the memory cell to be read, depending on whether the first current is larger than, smaller than, or equal to the second current.
A method for reading data, in a non-volatile semiconductor memory device comprising a plurality of memory cells and a plurality of reference cells, from the memory cell set in one of at least three states, wherein
- a first one of the reference cells is set so that a read current thereof coincides with a maximum or minimum value of a read current of the memory cell set in a first state,
- a second one of the reference cells is set so that a read current thereof coincides with a maximum or minimum value of a read current of the memory cell set in a second state, and
- the remaining reference cell or cells are set so that a read current thereof coincides with a predetermined value,
- the method comprising the steps of:
- obtaining a read current of the memory cell to be read as a first current;
- obtaining a second current based on the read current of the first reference cell and the read current of the second reference cell;
- obtaining a third current based on read currents of two of the reference cells other than the first reference cell;
- calculating a first comparison result, depending on whether the first current is larger than, smaller than, or equal to the second current;
- calculating a second comparison result, depending on whether the first current is larger than, smaller than, or equal to the third current;
- and
- calculating data stored in the memory cell to be read based on the first comparison result and the second comparison result.
A circuit for reading data from a non-volatile semiconductor memory device comprising a plurality of memory cells, the circuit comprising:
- a first reference cell set so that a read current thereof coincides with a maximum or minimum value of a read current of the memory cell set in a first state;
- a second reference cell set so that a read current thereof coincides with a maximum or minimum value of a read current of the memory cell set in a second state;
- a first current supply circuit of supplying a read current as a first current to the memory cell to be read;
- a second current supply circuit of supplying a second current based on the read current of the first reference cell and the read current of the second reference cell;
- and
- a comparison section of calculating data stored in the memory cell to be read, depending on whether the first current is larger than, smaller than, or equal to the second current.
A method for reading data, in a non-volatile semiconductor memory device comprising a plurality of memory cells and a plurality of reference cells, from the memory cell, wherein
- the memory cells are divided into a first type such that the memory cell is set to be one of at least four states on a block-by-block basis, and a second type such that the memory cell is set to be one of at least two states,
- each memory cell block is associated with at least four reference cells,
- the first to fourth reference cells of the first type memory cell are set so that respective read currents coincide with a maximum or minimum value of a read current of a memory cell set in one of the four states,
- the first and third reference cells of the second type memory cell are set so that respective read currents coincide with a maximum or minimum value of a read current of a memory cell set in one of the two states, and
- the second and fourth reference cells of the second type memory cell are set so that respective read currents coincide with a maximum or minimum value of a read current of a memory cell set in the other of the two states,
- the method comprising the steps of:
- obtaining a read current of the memory cell to be read as a first current;
- obtaining a second current based on the read current of the first reference cell and the read current of the second reference cell;
- obtaining a third current based on the read current of the second reference cell and the read current of the third reference cell;
- obtaining a fourth current based on the read current of the third reference cell and the read current of the fourth reference cell;
- and
- calculating data stored in the memory cell to be read, depending on whether the first current is larger than, smaller than, or equal to the second to fourth currents.
Dependencies are inferred from the claim text.